# US 5,710,739 A · Reading circuit for memory cells

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- Number: US 5,710,739 A
- Document ID: US5710739A
- Status: Granted
- Kind: A
- Application number: 08/476,547
- Filed: 1995-06-06
- Granted: 1998-01-20
- Earliest claimed: 1994-08-31
- Assignees: SGS-Thomson Microelectronics S.A.
- Inventors: Cristiano Calligaro; Roberto Gastaldi; Paolo Rolandi; Guido Torelli
- Web page: https://patentgrep.com/patent/US5710739A

## CPC

- G11C 7/065: {Differential amplifiers of latching type}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.

## Claims

### Claim 1

A memory read circuit for developing an output signal from a complementary pair of signal inputs, comprising:
two legs each connected between a positive supply voltage and a ground voltage;
each said leg consisting of a series connection of a clocked PMOS switch, an active element, and a switched PMOS load element; both said PMOS switches, and both said PMOS load elements, having gates thereof connected to a common clock signal;
said legs having said respective active elements thereof cross-coupled in a latch configuration to form a voltage amplifier; and
first and second input circuit elements, each connected to provide a load to one of the pair of complementary signal inputs, and to provide a corresponding voltage to a gate terminal of a respective one of said active elements.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein said input circuit elements each comprise a diode-connected transistor having a respective drain terminal thereof connected to a respective one of the signal inputs and to a respective gate terminal of the active element.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein said positive supply voltage is less than 5 Volts.

### Claim 4

A memory read circuit for developing an output signal from a complementary pair of signal inputs, comprising:
a first pair of PMOS transistors clocked by a first clock signal;
a second pair of PMOS transistors cross-coupled to form a latch;
a third pair of PMOS transistors clocked by said first clock signal;
said first, second, and third transistor pairs being mutually connected in two circuit legs between a positive supply voltage and a ground voltage, each said leg consisting of one respective transistor of said second pair of transistors, interposed between one respective transistor of said first pair of transistors and one respective transistor of said third pair of transistors; and
first and second input circuit elements, each connected to provide a load to one of the pair of complementary signal inputs, and to provide a corresponding voltage to a gate terminal of a respective one of said second pair of transistors.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein said input circuit elements each comprise a diode-connected transistor having a respective drain terminal thereof connected to a respective one of the signal inputs and to a respective gate terminal of the second pair of transistors.

### Claim 6 (depends on 4)

The circuit of claim 4, wherein said positive supply voltage is less than 5 Volts.