# US 5,710,735 A · EEPROM and method for fabricating the same

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- Number: US 5,710,735 A
- Document ID: US5710735A
- Status: Granted
- Kind: A
- Application number: 08/764,245
- Filed: 1996-12-12
- Granted: 1998-01-20
- Earliest claimed: 1994-07-18
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Ki Soo Shin; Soo Han Choi
- Web page: https://patentgrep.com/patent/US5710735A

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An EEPROM including a selecting gate which overlaps with one side of a floating gate and a certain part of a source electrode and a control gate which overlaps with the other side of the floating gate and a certain part of a drain electrode, is improved in charge coupling ratio, showing an increase in program efficiency even at low outer voltages. Application of low outer voltages to the EEPROM brings about a decrease in both the breakdown voltage and the junction breakdown voltage of the gate oxide film of peripheral transistors, allowing a shallow junction and a thin gate oxide film process to be possible. A shallow junction can be effected by an ion-implanting process which results in formation of a source electrode and a drain electrode.

## Claims

### Claim 1

An EEPROM, comprising:
a gate oxide film and a floating gate stacked on a semiconductor substrate;
a first interlayer insulating film formed on all exposed surfaces of the floating gate and the semiconductor substrate;
a selecting gate overlapping with the first interlayer insulating film from an upper surface of the floating gate to a portion of the semiconductor substrate;
a drain electrode and a source electrode formed in the semiconductor substrate which overlap with a portion of the floating gate and a portion of the selecting gate, respectively;
a second interlayer insulating film formed on all exposed surfaces of the first interlayer insulating film and the selecting gate;
a contact hole formed in the second interlayer insulating film, exposing the selecting gate; and
a control gate which is in touch with the selecting gate through the contact hole and shields a surface portion of the floating gate which is not overlapped by the selecting gate.

### Claim 2 (depends on 1)

An EEPROM in accordance with claim 1, wherein said floating gate is of island type overlapping with only an active region of the semiconductor substrate.

### Claim 3 (depends on 1)

An EEPROM in accordance with claim 1, wherein said selecting gate and said control gate are formed extending in one direction.

### Claim 4 (depends on 1)

An EEPROM in accordance with claim 1, wherein said first interlayer insulating film is structured to be either an oxide film monolayer or an oxide-nitride-oxide multilayer.