# US 5,710,731 A · Combined adder and decoder digital circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,710,731 A
- Document ID: US5710731A
- Status: Granted
- Kind: A
- Application number: 08/646,194
- Filed: 1996-05-07
- Granted: 1998-01-20
- Earliest claimed: 1996-05-07
- Assignees: International Business Machines Corporation
- Inventors: Michael Kevin Ciraula; Sang Hoo Dhong; Joel Abraham Silberman
- Web page: https://patentgrep.com/patent/US5710731A

## CPC

- G06F 7/57: Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An address used to access on-chip memory is calculated by summing two binary numbers to obtain an N-bit address. The N-bit address is decoded into a one-out-of-2.sup.N signal to select the addressed memory location. Instead of performing these operations sequentially, the addition and decoding are done at the same time, saving time and power and enabling changes to microprocessor organization and operation that enhance performance.

## Claims

### Claim 1

A combined adder/decoder circuit which combines the functions of addition and decoding, comprising:
a first decoder logic circuit for decoding a group of N binary bits of a first operand to a first one-out-of-2N output;
a second decoder logic circuit for decoding a group of N binary bits of a second operand to a second one-out-of-2N output; and
a shifter logic circuit for receiving said first one-out-of-2N output and shifting an active bit position of said first one-out-of-2N output left by a number of positions according to said second one-out-of-2N output thereby generating a decoded and summed one-out-of-2N output of said first and second operands, wherein said first and second operands are divided into several subgroups of a few adjacent bits and said first and second decoder logic circuits and said shifter logic circuit are divided into a tree-based decoder in which subgroups are decoded and added in a merged shifting and decoding operation, subgroups are divided from most significant bits to least significant bits and the shifter logic circuit of each subgroup, except for the most significant bits subgroup, is extended so that circular shifting does not occur in the event of a carry within in the subgroup, decoded and added subgroups are combined to generate said decoded and summed output of said first and second operands.

### Claim 2 (depends on 1)

The combined adder/decoder circuit recited in claim 1 wherein N is 6 and comprises three subgroups of 2-bits each, each of said three subgroups comprising said first decoder logic circuit, said second decoder logic circuit, and said shifter logic circuit said combined adder/decoder circuit further comprising logic for combining outputs of said first decoder logic circuit and second decoder logic circuit and said shifter logic circuit to generate said decoded and summed one-out-of-2.sup.N output.

### Claim 3 (depends on 2)

The combined adder/decoder circuit recited in claim 2 wherein a first subgroup of said three subgroups comprises:
a first group of four AND gates for producing a decoded output for the two most significant bits of said first operand;
a second group of four AND gates for producing a decoded output for the two most significant bits of said second operand; and
four groups each comprising four AND gates and an OR gate for receiving outputs of each of the four AND gates in the group, said AND gates of each group receiving selected outputs of the first and second group of AND gates and the OR gates of the four groups collectively generating an output representing a left shifting of an active bit of the decoded output of the first group of AND gates a number of positions represented by the decoded output of the second group of AND gates.

### Claim 4 (depends on 3)

The combined adder/decoder circuit recited in claim 3 wherein each of a second and third of said three subgroups, comprise:
a first group of four AND gates for producing a decoded output for two bits of said first operand;
a second group of four AND gates for producing a decoded output for two bits of said second operand; and
seven groups of AND gates divided into groups of one, two, three, four, three, two, and one AND gates, said groups comprising two, three, and four AND gates further comprising an OR gate for combining outputs of said AND gates, said AND gates of each group receiving selected outputs of the first and second group of AND gates and the groups of one AND gate each and the OR gates collectively generating an output representing a left shifting of an active bit of the decoded output of the first group of AND gates a number of positions represented by the decoded output of the second group of AND gates.