Pipeline analog to digital converter architecture with reduced mismatch error

An apparatus including a sample and hold circuit for use in a pipelined analog-to-digital converter for sampling and holding an input analog signal and providing an output analog residue signal, comprising:

• a logic circuit configured to receive a logic clock signal and a plurality of digital signal bits and in accordance therewith provide a plurality of control signals, wherein said digital signal bits include a plurality of bit patterns and represent an input analog signal which has been quantized in accordance with a plurality of reference signals;
• a plurality of reference signal ports configured to receive said plurality of reference signals;
• an input signal port configured to receive said input analog signal;
• an output signal port configured to receive an output analog residue signal;
• a sample signal port configured to receive an analog sample signal;
• a first switching port;
• a second switching port;
• a circuit reference port configured to provide a circuit ground reference;
• a first capacitance, coupled between said sample signal port and said first switching port;
• a second capacitance, coupled between said sample signal port and said second switching port;
• a signal routing circuit, coupled to said logic circuit and coupled between said sample signal port, said first switching port, said second switching port, said plurality of reference signal ports, said input signal port, said output signal port and said circuit reference port, configured to receive at least one routing clock signal and said plurality of control signals and in accordance therewith selectively couple said sample signal port to said circuit reference port, alternately couple said first switching port to said input signal port, said output signal port and said circuit reference port, and alternately couple said second switching port to said input signal port, said output signal port and individual ones of said plurality of reference signal ports and in accordance therewith provide said analog sample signal;
• and
• an amplifier, coupled between said sample signal port and said output signal port, configured to receive said analog sample signal and in accordance therewith provide said output analog residue signal;
• wherein:
• one of said plurality of bit patterns represents a range of values of a reference analog residue signal corresponding to a predetermined range of values of said input analog signal and having minimum and maximum reference analog residue signal values which are defined in accordance with said plurality of reference signals;
• said output analog residue signal includes a range of values between minimum and maximum output analog residue signal values;
• and
• said minimum and maximum output analog residue signal values are greater than and less than said minimum and maximum reference analog residue signal values, respectively.