# US 5,710,451 A · High-voltage lateral MOSFET SOI device having a semiconductor linkup region

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- Number: US 5,710,451 A
- Document ID: US5710451A
- Status: Granted
- Kind: A
- Application number: 08/629,819
- Filed: 1996-04-10
- Granted: 1998-01-20
- Earliest claimed: 1996-04-10
- Assignees: Philips Electronics North America Corporation
- Inventors: Steven L. Merchant
- Web page: https://patentgrep.com/patent/US5710451A

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 30/6733: {Multi-gate TFTs}
- H10D 64/111: {Field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region. This device configuration is particularly useful in providing a high-voltage p-channel MOS transistor using thin SOI high-voltage technology normally associated with fabricating n-channel devices.

## Claims

### Claim 1

A Semiconductor-On-Insulator (SOI) device comprising a semiconductor substrate, a buried insulating layer on said substrate, and a lateral MOSFET on said buried insulating layer, said MOSFET comprising a semiconductor surface layer on said buried insulating layer and having a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over said channel region and insulated therefrom, a lateral drift region of said second conductivity type, and a drain region of said first conductivity type and laterally spaced apart from said channel region by said drift region, characterized in that a semiconductor linkup region of said first conductivity type is provided between said channel region and said drift region and extends substantially through said semiconductor surface layer, and in that said source region is electrically coupled to said drift region.

### Claim 2 (depends on 1)

An SOI device as in claim 1, wherein said first conductivity type is p type and said second conductivity type is n type.

### Claim 3 (depends on 1)

An SOI device as in claim 1, wherein said first conductivity type is n type and said second conductivity type is p type.

### Claim 4 (depends on 1)

An SOI device as in claim 1, wherein said linkup region extends from an upper surface of said semiconductor surface layer down to said buried insulating layer.

### Claim 5 (depends on 1)

An SOI device as in claim 1, characterized in that at least a part of said lateral drift region between said linkup region and said drain region is thinner than a remaining part of said semiconductor surface layer.

### Claim 6 (depends on 1)

An SOI device as in claim 1, characterized in that a surface insulating layer is provided on said drift region, and in that a conductive field plate is provided on said surface insulating layer and over at least a part of said drift region, said conductive field plate being electrically coupled to said drain region.

### Claim 7 (depends on 1)

An SOI device as in claim 1, characterized in that a buffer region of said second conductivity type and having a higher doping concentration than that of said drift region is provided between said linkup region and said drift region.

### Claim 8 (depends on 1)

An SOI device as in claim 1, characterized in that said linkup region comprises a surface region of said first conductivity type and having a higher doping concentration than that of a remaining part of said linkup region.