# US 5,710,443 A · Merged device with aligned trench fet and buried emitter patterns

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- Number: US 5,710,443 A
- Document ID: US5710443A
- Status: Granted
- Kind: A
- Application number: 08/472,337
- Filed: 1995-06-07
- Granted: 1998-01-20
- Earliest claimed: 1995-02-28
- Assignees: SGS-Thompson Microelectronics S.A.
- Inventors: Richard A. Blanchard
- Web page: https://patentgrep.com/patent/US5710443A

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 84/01: Manufacture or treatment
- H10D 84/0158: {the components including FinFETs}
- H10D 84/121: {BJTs having built-in components}
- H10D 84/141: {VDMOS having built-in components}
- H10D 84/406: {Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/157: {Impurity concentrations or distributions}
- Y10S 148/126: Power FETs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.

## Claims

### Claim 1

A switched-emitter merged device structure, comprising:
a plurality of field-effect control transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and a gate connected to control the flow of carriers of said first conductivity type from said source region through a channel region downwardly into said semiconductor material; and
a plurality of power bipolar transistor portions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
wherein said emitter diffusion include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective control transistor portion, and said single base diffusion a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer; and
wherein individual ones of said emitter diffusions of said bipolar transistor portions are aligned to respective corresponding ones of said control transistor portions for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein said semiconductor material consists of silicon.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein said second buried layer has a dopant concentration per unit area which is greater than 5.times.10.sup.15 cm.sup.-2.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein said second buried layer has a dopant concentration per unit area which is greater than 1.times.10.sup.16 cm.sup.-2.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein said bipolar transistor has a beta of less than 50.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein said bipolar transistor has a base width which is greater than 1 micron.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein said bipolar transistor has an emitter doping concentration, in proximity to said base diffusion, which is less than three times the doping concentration of said base diffusion in proximity to said emitter diffusion.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein said first conductivity type is N-type.

### Claim 9

A switched-emitter merged device structure, comprising:
a plurality of field-effect trench transistor portions each comprising a source region of a first conductivity type near a first surface of a substantially monocrystalline semiconductor material, and an insulated gate connected to control the flow of carriers of said first conductivity type from said source region through a second-conductivity-type channel region along the wall of a trench downwardly into said semiconductor material; and
a plurality of power bipolar transistor potions each comprising an emitter diffusion of said first conductivity type overlying a portion of a single base diffusion of a second conductivity type;
wherein said emitter diffusions include a first buried layer having multiple separate spaced apart minimum-geometry emitter diffusion portions on the order of a respective trench transistor portion, and said single base diffusion includes a second buried layer which extends between and connects with adjacent emitter diffusion portions of said first buried layer;
and wherein said emitter diffusions are aligned in a pattern which predominantly corresponds to the pattern of said trenches for providing an increased emitter diffusion length per unit area such that a current density of said plurality of power bipolar transistor portions is maximized.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein said semiconductor material consists of silicon.

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein said second buried layer has a dopant concentration per unit area which is greater than 5.times.10.sup.15 cm.sup.-2.

### Claim 12 (depends on 9)

The integrated circuit of claim 9, wherein said second buried layer has a dopant concentration per unit area which is greater than 1.times.10.sup.16 cm.sup.-2.

### Claim 13 (depends on 9)

The integrated circuit of claim 9, wherein said bipolar transistor has a beta of less than 50.

### Claim 14 (depends on 9)

The integrated circuit of claim 9, wherein said bipolar transistor has a base width which is greater than 1 micron.

### Claim 15 (depends on 9)

The integrated circuit of claim 9, wherein said bipolar transistor has an emitter doping concentration, in proximity to said base diffusion, which is less than three times the doping concentration of said base diffusion in proximity to said emitter diffusion.

### Claim 16 (depends on 9)

The integrated circuit of claim 9, wherein said first conductivity type is N-type.