# US 5,710,442 A · Semiconductor device and method of manufacturing same

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- Number: US 5,710,442 A
- Document ID: US5710442A
- Status: Granted
- Kind: A
- Application number: 08/589,637
- Filed: 1996-01-22
- Granted: 1998-01-20
- Earliest claimed: 1995-02-03
- Assignees: Hitachi, Ltd.
- Inventors: Atsuo Watanabe; Katsuaki Saito
- Web page: https://patentgrep.com/patent/US5710442A

## CPC

- H10D 18/00: Thyristors
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/206: {Cathode base regions of thyristors}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device sets an impurity density of a p base layer in a bevel end-face region to a density lower than that in an operating region and has a parasitic channel preventive region provided between the bevel end-face region and the operating region. Since the blocking-voltage and the current-carrying capacity can be adjusted independently from each other, the blocking voltage and the current-carrying capacity can be both improved.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor base substrate having a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer located on the first semiconductor layer, a first conductivity type third semiconductor layer located on the second semiconductor layer and a second conductivity type fourth semiconductor layer located on the third semiconductor layer, the semiconductor base substrate including a first region adjacent to an end of said semiconductor base substrate and a second region provided inside the first region;
a first main electrode provided on the first semiconductor layer; and
a second main electrode provided on the fourth semiconductor layer,
said third semiconductor layer in the first region having an average impurity density smaller than that of the third semiconductor layer in the second region, and
said second main electrode being in contact with the third semiconductor layer between the first and second regions,
wherein a parasitic channel preventive region is provided between the first and second regions, the parasitic channel preventive region having a width greater than or equal to a diffusion length of a minority carrier in the second semiconductor layer.

### Claim 2 (depends on 1)

A semiconductor device according to claim 1, wherein the first region has a bevel structure.

### Claim 3 (depends on 1)

A semiconductor device according to claim 1, wherein the average impurity density of the third semiconductor layer in the first region is approximately 10.sup.14 cm.sup.-3.

### Claim 4 (depends on 1)

A semiconductor device according to claim 1, wherein a surface impurity density of the third semiconductor layer is approximately 10.sup.16 cm.sup.-3 in the first region and approximately 10.sup.16 cm.sup.-3 in the second region.

### Claim 5 (depends on 1)

A semiconductor device according to claim 1, wherein a sheet resistivity of the third semiconductor layer is about 1,000 .OMEGA./.quadrature. in the first region and about 300 .OMEGA./.quadrature. in the second region.

### Claim 6 (depends on 2)

A semiconductor device according to claim 2, wherein a side face of the first region has two portions at which two pn-junctions are exposed, and wherein the bevel structure has a positive bevel in each of said two portions.

### Claim 7

A semiconductor device comprising:
a semiconductor base substrate having a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer located on the first semiconductor layer, a first semiconductor type third semiconductor layer located on the second semiconductor layer and a second conductivity type fourth semiconductor layer located on the third semiconductor layer, the semiconductor base substrate including a first region adjacent to an end of said semiconductor base substrate and a second region provided inside the first region;
a first main electrode provided on the first semiconductor layer; and
a second main electrode provided on the fourth semiconductor layer,
said third semiconductor layer in the first region having an average impurity density smaller than that of the third semiconductor layer in the second region, and
said second main electrode being in contact with the third semiconductor layer between the first and second regions,
wherein a parasitic channel preventive region is provided between the first and second regions, and
wherein a first conductivity type fifth semiconductor layer having an impurity density higher than that of the first region is provided on the surface of the third semiconductor layer in the parasitic channel preventive region.

### Claim 8 (depends on 7)

A semiconductor device according to claim 7, wherein said second main electrode makes contact with the fifth semiconductor layer.

### Claim 9 (depends on 7)

A semiconductor device according to claim 7, wherein the first region has a bevel structure.

### Claim 10 (depends on 9)

A semiconductor device according to claim 9, wherein a side face of the first region has two portions at which two pn-junctions are exposed, and wherein the bevel structure has a positive bevel in each of said two portions.

### Claim 11 (depends on 10)

A semiconductor device according to claim 10, wherein said second main electrode makes contact with the fifth semiconductor layer.

### Claim 12 (depends on 9)

A semiconductor device according to claim 9, wherein said second main electrode makes contact with the fifth semiconductor layer.