# US 5,710,379 A · Apparatus and method for determining a flow count > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,379 A - Document ID: US5710379A - Status: Granted - Kind: A - Application number: 08/720,791 - Filed: 1996-10-04 - Granted: 1998-01-20 - Earliest claimed: 1996-10-04 - Assignees: Dieterich Technology Holding Corp. - Inventors: Alvin E. Brown - Web page: https://patentgrep.com/patent/US5710379A ## CPC - G01F 1/667: Arrangements of transducers for ultrasonic flowmeters; Circuits for operating ultrasonic flowmeters - G01F: MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME ## Abstract An apparatus for determining a flow count in an ultrasonic flow meter has an upstream oscillator (22) with an upstream signal (24) having a period proportional to an upstream transit time and a downstream oscillator (26) with a downstream signal (28) having a period proportional to a downstream transit time. The upstream signal (24) is coupled to a positive increment input (30) of a counter (32) and the downstream signal (28) is coupled to a negative increment input (36) the counter (32). ## Claims ### Claim 1 An apparatus for determining a flow count in an ultrasonic flow meter comprising: an upstream oscillator having an upstream signal with a period proportional to an upstream transit time; a downstream oscillator having a downstream signal with a period proportional to a downstream transit time; and a counter having a positive increment input coupled to the upstream signal, a negative increment input coupled to the downstream signal and an output with a counter signal proportional to the flow count. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the positive increment input is a positive period of a counter control signal. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the negative increment input is a negative period of a counter control signal. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the counter is an up-down counter. ### Claim 5 (depends on 1) The apparatus of claim 1, further including a synchronization and hold circuit having a pair of inputs coupled to the upstream signal and the downstream signal. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein an output of the synchronization and hold circuit is true during a positive period of a counter control signal, if a positive going edge of the upstream signal occurs between a first falling edge before the positive period and an end of the positive period. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein an output of the synchronization and hold circuit is true during a negative period of the counter control signal, if a positive going edge of the downstream signal occurs between a first rising edge before the negative period and an end of the negative period. ### Claim 8 (depends on 1) The apparatus of claim 1, further including a latch coupled to an output of the counter. ### Claim 9 (depends on 9) The apparatus of claim 9, wherein the output of the latch is coupled to a microprocessor. ### Claim 10 A method for determining a flow data count in an ultrasonic flow meter, comprising the steps of: (a) adjusting a period of an upstream signal to be an integer divisor of an upstream transit time; (b) adjusting a period of a downstream signal to be an integer divisor of a downstream transit time; (c) counting the periods of the upstream signal to form an up count; (d) counting the periods of the downstream signal to form a down count; and (e) subtracting the down count from the up count to form a count signal proportional to the flow data count. ### Claim 11 (depends on 10) The method of claim 10, further including the steps of: (f) sampling the count signal to form a sample; (g) storing the sample. ### Claim 12 (depends on 11) The method of claim 11, further including the step of: (h) retrieving the sample by a microprocessor. ### Claim 13 An apparatus for determining a flow data count in an ultrasonic flow meter, comprising: an up-down counter having a positive increment input coupled to an upstream signal and a negative increment input coupled a downstream signal; and a latch circuit coupled to an output of the counter. ### Claim 14 (depends on 13) The apparatus of claim 13, further including a synchronization and hold circuit having a pair of inputs, one of the pair of inputs coupled to the upstream signal and a second of the pair of inputs coupled to the downstream signal. ### Claim 15 (depends on 14) The apparatus of claim 14, further including a counter control signal having a frequency at least twice a maximum frequency of the downstream signal, the counter control signal coupled to the synchronization and hold circuit and the up-down counter. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the synchronization and control circuit has an output that is true during a positive portion of the counter control signal when a positive going edge of the upstream signal occurs between a first falling edge before the positive portion and an end of the positive portion. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the synchronization and control circuit has an output that is true during a negative portion of the counter control signal when a positive going edge of the downstream signal occurs between a first rising edge before the negative portion and an end of the negative portion. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the up-down counter increments when the counter control signal is in the positive portion and the output of the synchronization and control circuit is true. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the up-down counter decrements when the counter control signal is in the negative portion and the output of the synchronization and control circuit is true. ### Claim 20 (depends on 13) The apparatus of claim 13, wherein the latch circuit periodically samples the output of the up-down counter. ### Claim 21 (depends on 20) The apparatus of claim 20, where an output of the latch circuit is polled by a microprocessor.