# US 5,708,880 A · CMOS-analog IC for controlling camera and camera system using the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,708,880 A
- Document ID: US5708880A
- Status: Granted
- Kind: A
- Application number: 08/664,316
- Filed: 1996-06-07
- Granted: 1998-01-13
- Earliest claimed: 1993-03-16
- Assignees: Olympus Optical Co., Ltd.
- Inventors: Keiji Kunishige; Azuma Miyazawa
- Web page: https://patentgrep.com/patent/US5708880A

## CPC

- G03B 7/081: Analogue circuits
- G03B 7/091: Digital circuits
- G03B: APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR (optical parts of such apparatus G02B; photosensitive materials or processes for photographic purposes G03C; apparatus for processing exposed photographic materials G03D)

## Abstract

In a camera controller using a CMOS-analog-IC, a microcomputer, logarithmic compression type distance measuring and photometric circuits, each constituted by a CMOS device having a parasitic bipolar transistor having a p- or n-type well as a base and an n.sup.+ -type layer in the p-type well or p.sup.+ -type layer in the n-type well as an emitter, and the like are arranged on the same chip.

## Claims

### Claim 1

A CMOS integrated circuit for controlling a camera having various elements, comprising:
a one-chip microcomputer having a CMOS structure and a core portion for controlling the various elements in said camera; and
an analog distance measuring circuit having a CMOS structure and arranged in said one-chip microcomputer,
wherein the core portion of said one-chip microcomputer outputs a control signal to said analog distance measuring circuit.

### Claim 2 (depends on 1)

A circuit according to claim 1, wherein said distance measuring circuit is connected to a light-receiving element arranged outside said one-chip microcomputer.

### Claim 3 (depends on 1)

A circuit according to claim 1, wherein said distance measuring circuit generates a logarithmically compressed or expanded signal by using at least one of a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor in the CMOS structure.

### Claim 4 (depends on 3)

A circuit according to claim 3, wherein said distance measuring circuit has a difference calculating circuit for calculating a difference between the logarithmically compressed signals, and obtains an object distance on the basis of an output from said difference calculating circuit.

### Claim 5 (depends on 3)

A circuit according to claim 3, wherein at least one of said parasitic PNP bipolar transistor and said parasitic NPN bipolar transistor is transistor arranged between a substrate and electrode of an analog circuit having the MOS structure.

### Claim 6 (depends on 1)

A circuit according to claim 1, wherein said distance measuring circuit performs at least one of logarithmic compression and logarithmic expansion, based on a collector-grounded transistor.

### Claim 7 (depends on 1)

A circuit according to claim 1, wherein said distance measuring circuit includes a transistor, having a MOS structure, for outputting at least one of logarithmically compressed and expanded signals by using a weak inversion region.

### Claim 8

A CMOS integrated circuit for controlling a camera having various elements, comprising:
a one-chip microcomputer having a CMOS structure and a core portion for controlling the various elements in said camera; and
an analog photometric circuit having a MOS structure and arranged in said one-chip microcomputer,
wherein the core portion of said one-chip microcomputer outputs a control signal to said analog photometric circuit.

### Claim 9 (depends on 8)

A circuit according to claim 8, wherein said photometric circuit is connected to a light-receiving element arranged outside said one-chip microcomputer.

### Claim 10 (depends on 8)

A circuit according to claim 8, wherein said photometric circuit generates a logarithmically compressed or expanded signal by using at least one of a parasitic PNP bipolar transistor and a parasitic NPN bipolar transistor in the CMOS structure.

### Claim 11 (depends on 10)

A circuit according to claim 10, wherein said photometric circuit obtains an object brightness on the basis of the logarithmically compressed signal.

### Claim 12 (depends on 10)

A circuit according to claim 10, wherein at least one of said parasitic PNP bipolar transistor and said parasitic NPN bipolar transistor is a vertical transistor arranged between a substrate and electrode of an analog circuit having the MOS structure.

### Claim 13 (depends on 8)

A circuit according to claim 8, wherein said distance measuring circuit performs at least one of logarithmic compression and logarithmic expansion, based on a collector-grounded transistor.

### Claim 14 (depends on 8)

A circuit according to claim 8, wherein said photometric circuit includes a transistor, having a MOS structure, for outputting at least one of logarithmically compressed and expanded signals by using a weak inversion region.