# US 5,708,852 A · Apparatus for serial port with pattern generation using state machine for controlling the removing of start and stop bits from serial bit data stream

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- Number: US 5,708,852 A
- Document ID: US5708852A
- Status: Granted
- Kind: A
- Application number: 08/510,080
- Filed: 1995-08-01
- Granted: 1998-01-13
- Earliest claimed: 1995-08-01
- Assignees: International Business Machines Corporation
- Inventors: Donna Wiltsey Aebli; James Norris Dieffenderfer
- Web page: https://patentgrep.com/patent/US5708852A

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A serial port having a pattern generation mode and a microprocessor using same. The serial port uses a transmit circuit controlled by a state machine which determines whether start and stop bits are transmitted by a computer implemented method. In pattern generation mode, start and stop bits are not transmitted, and the serial port lends itself to transmitting pulse width modulation data. In one embodiment, the serial port is used in a microprocessor which includes a central processing unit (CPU) and a bus interface unit.

## Claims

### Claim 1

A transmit circuit for a serial port with a pattern generation mode, the transmit circuit comprising:
an enable terminal;
a frame control terminal;
an output terminal;
a transmit buffer for storing un-framed data to be transmitted;
frame determination logic connected to the frame control terminal and the transmit buffer, the frame determination logic for determining a data frame to be transmitted;
a transmit shift register for storing a frame to be transmitted;
a transmit multiplexer disposed between the frame determination logic and the transmit shift register, the transmit multiplexer receiving as inputs an output from the shift register and an output from the frame determination logic;
bit determination logic disposed between the shift register and a latch, the bit determination logic for determining a next bit to be transmitted; and
a state machine connected to the transmit multiplexer, the frame determination logic, the transmit shift register and the bit determination logic, the state machine controlling the data flow from the transmit buffer to the latch so that start and stop bits can be removed from the data and the beginning and ending of frames can be monitored in a pattern generation mode.

### Claim 2 (depends on 1)

The transmit circuit of claim 1 wherein the state machine further comprises:
a baud rate clock terminal
a transmit counter;
state machine control logic connected to the baud rate clock terminal for controlling the transmit multiplexer and the shift register;
a decrementer disposed between the transmit counter and the state machine control logic;
count value determination logic connected to the frame control terminal and the enable terminal; and
a count multiplexer disposed between the count value determination logic and the transmit counter, the count multiplexer being controlled by the state machine control logic and receiving as inputs an output from the count value determination logic and an output from the decrementer.

### Claim 3

A microprocessor having a serial port with pattern generation mode, the microprocessor comprising:
bus interfaces;
a serial interface;
a central processing unit (CPU) for performing computations and controlling data flow;
a bus interface unit disposed between the CPU and the bus interfaces; and
a serial port disposed between the bus interface unit and the serial interface, the serial port having a transmit circuit further including:
an enable terminal;
a frame control terminal;
an output terminal;
a transmit buffer for storing un-framed data to be transmitted;
frame determination logic connected to the frame control terminal and the transmit buffer, the frame determination logic for determining a data frame to be transmitted;
a transmit shift register for storing a frame to be transmitted;
a transmit multiplexer disposed between the frame determination logic and the transmit shift register, the transmit multiplexer receiving as inputs an output from the shift register and an output from the frame determination logic;
bit determination logic disposed between the shift register and a latch, the bit determination logic for determining a next bit to be transmitted; and
a state machine connected to the transmit multiplexer, the frame determination logic, the transmit shift register and the bit determination logic, the state machine controlling the data flow from the transmit buffer to the latch so that start and stop bits can be removed from the data and the beginning and ending of frames can be monitored in a pattern generation mode.

### Claim 4 (depends on 3)

The microprocessor of claim 3 wherein the state machine further comprises:
a baud rate clock terminal;
a transmit counter;
state machine control logic connected to the baud rate clock terminal for controlling the transmit multiplexer and the shift register;
a decrementer disposed between the transmit counter and the state machine control logic;
count value determination logic connected to the frame control terminal and the enable terminal; and
a count multiplexer disposed between the count value determination logic and the transmit counter, the count multiplexer being controlled by the state machine control logic and receiving as inputs an output from the count value determination logic and an output from the decrementer.

### Claim 5 (depends on 3, 4)

The microprocessor according to claims 3 or 4 further comprising:
an interrupt interface;
a direct memory access (DMA) control interface;
a DMA controller disposed between the bus interface unit and the DMA control interface; and
an interrupt controller disposed between the CPU and the interrupt interface.

### Claim 6

A computer implemented method of operating a serial port with a pattern generation mode, the method comprising the steps of:
initializing the serial port;
waiting for data to be written to a transmit buffer;
loading data from the transmit buffer to a shift register;
determining if the pattern generation mode of the serial port is enabled;
if the pattern generation mode of the serial port is enabled, setting a first bit to transmit to be a bit after a start bit;
if the pattern generation mode of the serial port is enabled, loading a count into a transmit counter, so that the transmit counter does not count a stop bit;
transmitting a bit;
decrementing the transmit counter;
shifting the shift register;
determining if a transmit count is equal to zero; and
if the transmit count is not equal to zero, transmitting a bit.

### Claim 7 (depends on 6)

The method of claim 6 further comprising the steps of:
if the pattern generation mode of the serial port is not enabled, setting the first bit to transmit to be the start bit; and
if the pattern generation mode of the serial port is not enabled, loading a count into the transmit counter so that the counter counts the stop bit.

### Claim 8 (depends on 6)

The method according to claim 6 further comprising the steps of:
if the transmit count is equal to zero, determining if the transmit buffer contains additional data; and
if the transmit buffer contains additional data, loading the shift register.

### Claim 9 (depends on 8)

The method according to claim 8 further comprising the step of:
if the transmit buffer does not contain additional data, waiting for data to be written to the transmit buffer.

### Claim 10 (depends on 7)

The method according to claim 7 further comprising the steps of:
if the transmit count is equal to zero, determining if the transmit buffer contains additional data; and
if the transmit buffer contains additional data, loading the shift register.

### Claim 11 (depends on 10)

The method according to claim 10 further comprising the step of:
if the transmit buffer does not contain additional data, waiting for data to be written to the transmit buffer.