Implementing scatter/gather operations in a direct memory access device on a personal computer

A direct memory access circuit (DMA) circuit comprising:

• a first register for storing an address for data,
• a second register for storing a count of data at the address in the first register,
• a circuit for incrementing the address in the first register and decrementing the count in the second register until all data in a DMA transfer step has been transferred,
• a pointer register for holding an address of an entry in an entry list, each entry therein including:
• an address value,
• a byte count value according to which a DMA transfer step is to be performed, and
• a last entry bit indicating whether the entry is last in the entry list, and
• a state machine for controlling operations of the DMA circuit including:
• a first portion for transferring data from one address to another, and
• a second portion for transferring an entry at the address held in the pointer register to the DMA circuit and an address in the entry to the first register and for sensing the last entry bit, the second portion functioning in response to:
• an indication that the DMA transfer step has been initiated, and
• the last entry bit.

An computer system comprising:

• a central processing unit;
• main memory;
• a bus for transferring data and addresses coupled to the central processing unit and the main memory;
• and a direct memory access (DMA) coupled to the bus, the DMA circuit comprising:
• first means for storing a starting address in memory for a list of entries, each entry including addresses and counts of the amount of data included at each address, each entry further including a designation bit, setting of the bit indicating an entry is a last entry in the list;
• second means for storing an address for data to be transferred by the direct memory access circuit;
• third means for retrieving a subsequent entry from said list including means to transfer the address to the second means;
• fourth means responsive to any address in the memory for a list of entries for transferring an entry from said list to the second means for storing an address;
• fifth means responsive to an address in the second means for sequentially transferring data beginning at the address in the second means, the fifth means also for incrementing an address in the second means and transferring data until the count of the amount of data is exhausted;
• sixth means for sensing that data at an address on the list of entries has yet to be transferred;
• and
• seventh means for incrementing the address held by the first means and for causing the third means to respond, while said fifth means is active, to the address in the first means and transfer the subsequent entry from the list of entries to the second means so long as entries at addresses on the list of entries have yet to be transferred and said fifth means has completed transfer of all data.

An direct memory access (DMA) circuit for use in a computer system comprising:

• first means for storing a starting address in memory for a list of entries, each entry including addresses and counts of the amount of data included at each address, each entry further including a designation bit, setting of the bit indicating an entry is a last entry in the list;
• second means for storing an address for data to be transferred by the direct memory access circuit;
• third means for retrieving a subsequent entry from said list including means to transfer the address to the second means;
• fourth means responsive to any address in the memory for a list of entries for transferring an entry from said list to the second means;
• fifth means responsive to an address in the second means for sequentially transferring data beginning at the address in the second means, includes means for incrementing an address in the second means and transferring data until the count of the amount of data is exhausted;
• sixth means for sensing that data at an address on the list of entries has yet to be transferred;
• and
• seventh means for incrementing the address held by the first means and for causing the third means to respond, while said fifth means is active, to the address in the first means and transfer the subsequent entry from the list of entries to the second means, so long as entries at addresses on the list of entries have yet to be transferred and said fifth means has completed transfer of all data.

A method for performing a direct memory access (DMA) operation, comprising:

• a) loading a pointer register with an indication of the address within a memory of a first DMA entry;
• b) retrieving from the first DMA entry a first address indication and a first byte count indication;
• c) advancing the contents of the pointer register to indicate the address of a subsequent DMA entry;
• d) transferring data, in a first DMA transfer step, according to the first address indication and the first byte count indication;
• e) retrieving from the subsequent DMA entry, a subsequent address indication, a subsequent byte count indication and a last-entry bit, the retrieving occurring after initiating the current DMA transfer step and prior to completing it;
• f) transferring data, in a subsequent DMA transfer step, according to the subsequent address indication and the subsequent byte count indication;
• and g) when the last-entry bit is false, advancing the contents of the pointer register to indicate the location of another subsequent DMA entry and repeating the steps (e) through (g).

A direct memory access (DMA) controller system, comprising:

• a) a pointer register configured to contain an indication of the address within a memory of a current one of a plurality of DMA entries, each DMA entry including an address indication, a byte count indication and a last-entry bit;
• b) a base address register configured to retrieve from the memory the address indication from the current DMA entry;
• c) a base byte count register configured to retrieve from the memory the byte count indication from the current DMA entry;
• and
• d) means for transferring data, in a DMA transfer step, based on the address indication in the base address count register and the byte count indication in the base byte count register;
• when the last-entry bit of the previous DMA entry is false, said base address register and said base byte count register being configured to retrieve another address indication and another byte count indication after the DMA transfer means initiates the current DMA transfer step and prior to completing the same.