# US 5,708,835 A · Dual-directional parallel processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,835 A - Document ID: US5708835A - Status: Granted - Kind: A - Application number: 08/411,114 - Filed: 1995-03-27 - Granted: 1998-01-13 - Earliest claimed: 1995-03-27 - Assignees: Hughes Electronics Corporation - Inventors: Robert W. Burnett - Web page: https://patentgrep.com/patent/US5708835A ## CPC - G06F 15/17381: {Two dimensional, e.g. mesh, torus} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A dual-directional parallel processor. The inventive processor (10) includes an array (20) of processing elements (30). Each processing element has a first circuit (31) for inputting and outputting data, a second circuit (32) for inputting and outputting data; and a third circuit (33, 34) for setting the first circuit (31) in an input mode and for setting the second circuit (32) in an output mode in response to a first mode control signal. The third circuit (33, 34) also sets the first circuit (31) in an output mode and the second circuit (32) in an input mode in response to a second mode control signal. In the illustrative embodiment, data is communicated between the first and the second circuits (31, 32) and the processor further includes a fifth circuit (12) for inputting data to the array and a sixth circuit (14) for outputting data from the array. Each of the processing elements (30) is connected either between two other processing elements or between the fifth circuit (12) or the sixth circuit (14) and a neighboring processing element via the first or the second circuit (31 or 32) thereof. ## Claims ### Claim 1 A dual-directional parallel processor comprising: an array of processing elements, each processing element having: first means for inputting and outputting data, said first means including a first terminal, a first circuit for inputting data to said first terminal, and a second circuit for outputting data from said first terminal; second means for inputting and outputting data, said second means including a second terminal, a third circuit for inputting data to said second terminal and a fourth circuit for outputting data from said second terminal, an input of first circuit being connected to an output of said fourth circuit and an output of said second circuit being connected to an input to said third circuit; and third means for setting said first means in a first mode and for setting said second means in a second mode in response to a first mode control signal and for setting said first means in said second mode and for setting said second means in said first mode in response to a second mode control signal, whereby data is received by said processing element at said first terminal, communicated from said first terminal to said second terminal via said second circuit and said third circuit and output from said processing element by said second terminal in said first mode and received by said processing element at said second terminal, communicated from said second terminal to said first terminal via said fourth circuit and said first circuit and output from said processing element by said first terminal in said second mode. ### Claim 2 (depends on 1) The invention of claim 1 further including fourth means for communicating data between said first means and said second means. ### Claim 3 (depends on 1) The invention of claim 1 further including means for providing said mode control signals. ### Claim 4 (depends on 3) The invention of claim 3 wherein said means for providing said mode control signals is an instruction sequencer. ### Claim 5 (depends on 4) The invention of claim 4 further including means for decoding and executing instructions from said instruction sequencer. ### Claim 6 (depends on 5) The invention of claim 5 further including means for routing said mode control signals to said first means and said second means. ### Claim 7 (depends on 1) The invention of claim 1 wherein said processor further includes fifth means for inputting data to said array and sixth means for outputting data from said array. ### Claim 8 (depends on 7) The invention of claim 7 wherein each of said processing elements is connected either between two other processing elements or between said fifth means or said sixth means and a processing element via the first or the second means thereof. ### Claim 9 A dual-directional parallel processor comprising: an array of processing elements, each processing element having: first means for inputting and outputting data, said first means including a first terminal, a first circuit for inputting data to said first terminal, and a second circuit for outputting data from said first terminal; second means for inputting and outputting data, said second means including a second terminal, a third circuit for inputting data to said second terminal and a fourth circuit for outputting data from said second terminal, an input of first circuit being connected to an output of said fourth circuit and an output of said second circuit being connected to an input to said third circuit; third means for setting said first means in an input mode and for setting said second means in an output mode in response to a first mode control signal and for setting said first means in an output mode and for setting said second means in an input mode is response to a second mode control signal, whereby data is received by said processing element at said first terminal, communicated from said first terminal to said second terminal via said second circuit and said third circuit and output from said processing element by said second terminal in said first mode and received by said processing element at said second terminal, communicated from said second terminal to said first terminal via said fourth circuit and said first circuit and output from said processing element by said first terminal in said second mode and fourth means for communicating data between said first means and said second means; and fifth means for inputting data to said array and sixth means for outputting data from said array, wherein each of said processing elements is connected either between two other processing elements or between said fifth means or said sixth means and a processing element via the first or the second means thereof.