# US 5,708,815 A · DMA emulation via interrupt muxing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,815 A - Document ID: US5708815A - Status: Granted - Kind: A - Application number: 08/437,091 - Filed: 1995-05-05 - Granted: 1998-01-13 - Earliest claimed: 1995-05-05 - Assignees: Intel Corporation - Inventors: David I. Poisner - Web page: https://patentgrep.com/patent/US5708815A ## CPC - G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for coordinating DMA between memory and a peripheral on a bus which does not support DMA comprises DMA emulation circuitry in the peripheral which allows the internal modules of the peripheral to share a single shared interrupt output line. An emulation device driver assists the microprocessor in determining the cause of interrupt signals received by the shared interrupt output line and how to service the interrupt. ## Claims ### Claim 1 A peripheral, comprising: a first and second internal module, wherein the first internal module is a DMA coordinator; a first output line, coupled to the first internal module, that transmits a DMA request signal asserted by the fast internal module; a second output line, coupled to the second internal module, that transmits an interrupt signal asserted by the second internal module; an interrupt output circuit, coupled to the first output line and the second output line, that outputs a single interrupt signal on a shared interrupt output line to a microprocessor when the DMA request signal or the interrupt signal is asserted; and an interrupt recording unit, coupled to the first output line and the second output line, that records which of the first and second internal module is an initiator of the single interrupt signal. ### Claim 2 (depends on 1) The peripheral of claim 1, wherein the microprocessor coordinates data transfer between the peripheral and a memory. ### Claim 3 (depends on 1) The peripheral of claim 1 further comprising a bus master that generates addresses in memory to be accessed by the peripheral. ### Claim 4 (depends on 3) The peripheral of claim 3, wherein the microprocessor programs the bus master with addresses in memory to be accessed by the peripheral. ### Claim 5 (depends on 3) The peripheral of claim 3, wherein the bus master monitors a channel in a DMA controller for addresses in memory to be accessed. ### Claim 6 (depends on 1) The peripheral of claim 1, wherein said interrupt output circuit is an OR gate. ### Claim 7 A computer system, comprising: a memory comprising a plurality of buffers that store data; a microprocessor coupled to the memory; a memory controller that bridges the memory and the microprocessor to a bus; a peripheral device, coupled to the bus, comprising a first and second internal module, wherein the first internal module is a DMA coordinator, a first output line, coupled to the first internal module, that transmit a DMA request signal asserted by the first internal module, a second output line, coupled to the second internal module, that transmit a interrupt signal asserted by the second internal module, an interrupt output circuit, coupled to the first output line and the second output line, that outputs a single interrupt signal on a shared interrupt output line to a microprocessor when the DMA request signal or the interrupt signal is asserted, and an interrupt recording unit, coupled to the first output line and the second output line, that records which of the first and second internal module is an initiator of the single interrupt signal. ### Claim 8 (depends on 7) The computer system of claim 7, wherein the microprocessor coordinates data transfer between the peripheral and the memory. ### Claim 9 (depends on 7) The computer system of claim 7 further comprising a bus master that generates addresses in memory to be accessed. ### Claim 10 (depends on 9) The computer system of claim 9, wherein the microprocessor programs the bus master with addresses in memory to be accessed by the peripheral. ### Claim 11 (depends on 9) The computer system of claim 9, wherein the bus master monitors a channel of a DMA controller for addresses in the memory to be accessed. ### Claim 12 (depends on 7) The computer system of claim 7, wherein said interrupt output circuit is an OR gate. ### Claim 13 A method for managing interrupt signals in a microprocessor, comprising: determining a source of an interrupt signal; programming and starting a bus master if the source of the interrupt signal is a DMA coordinator module; restoring a DMA controller if the source of the interrupt signal is a bus master; and beginning an interrupt service murine if the interrupt comes from a source other than the DMA coordinator module or a bus master. ### Claim 14 (depends on 13) The method of claim 13, wherein determining a source of the interrupt signal is achieved by reading an interrupt recording unit in a peripheral. ### Claim 15 (depends on 13) The method of claim 13, wherein programming the bus master is achieved by writing memory addresses of buffers that are to be accessed in registers in the bus master. ### Claim 16 (depends on 13) The method of claim 13, wherein restoring the DMA controller is achieved by updating a length field counter in the DMA controller to indicate a data transfer. ### Claim 17 A circuit for managing interrupt signals, comprising: a interrupt source determinator that determines a source of an interrupt; a interrupt service routine initiator that starts an interrupt serve routine in memory when the source of the interrupt is not a DMA coordinator module; a bus master programmer, coupled to the interrupt service routine initiator, that sends memory addresses of buffers that are to be accessed by a peripheral to a bus master; and a DMA controller restorer, coupled to the bus master programmer, that updates a length field counter in a DMA controller to indicate a completed data transfer. ### Claim 18 (depends on 17) The circuit of claim 17, wherein said interrupt source determinator further comprises a circuit for reading an interrupt recording unit in a peripheral. ### Claim 19 (depends on 17) The circuit of claim 17, wherein said bus master programmer further comprises a circuit for reading registers in a DMA controller to retrieve memory address of buffers that are to be accessed by the peripheral.