# US 5,708,813 A · Programmable interrupt signal router

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- Number: US 5,708,813 A
- Document ID: US5708813A
- Status: Granted
- Kind: A
- Application number: 08/353,759
- Filed: 1994-12-12
- Granted: 1998-01-13
- Earliest claimed: 1994-12-12
- Assignees: Digital Equipment Corporation
- Inventors: Hoe To Cho; Ming Huann Yuan
- Web page: https://patentgrep.com/patent/US5708813A

## CPC

- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In a computer system, a random access memory of an interrupt router is programmed to store data as bit patterns at a plurality of memory locations. Each bit pattern correspond to a specific routing from a plurality of sources to a fixed number of interrupt input lines. The number of bits in each bit pattern equivalent to the number of interrupt input lines. The addresses of the memory, during operation, being selected by the interrupt signals generated by a plurality of interrupt sources.

## Claims

### Claim 1

An apparatus for routing interrupt signals in a computer system, comprising:
a memory having a plurality of addresses, each of the plurality of addresses to access a bit pattern stored at the corresponding address of the memory;
a plurality of interrupt lines for connecting interrupt sources to the memory, the plurality of interrupt lines configured as address lines of the memory, the plurality of interrupt lines to randomly access the plurality of addresses of the memory;
latch means, responsive to interrupt signals on the plurality of interrupt lines, to store a specific address of the memory, the specific address formed from the interrupt signals on the plurality of interrupt lines; and
means for transmitting to an interrupt processor the bit pattern stored at the specific address stored in the latch.

### Claim 2

An apparatus for routing interrupt signals in a computer system, comprising:
a random access memory having a plurality of cells, each cell randomly accessible by an address;
a plurality of interrupt lines for connecting to interrupt sources, the plurality of interrupt lines configured to address the plurality of cells of the random access memory;
latch means, responsive to interrupt signals generated by the interrupt sources, to store a specific address of the random access memory, the specific address formed from the interrupt signals on the plurality of interrupt lines; and
means for transmitting to an interrupt processor a bit pattern stored in the cell of the random access memory accessed by the specific address.

### Claim 3 (depends on 2)

The apparatus of claim 2 further comprising:
means for writing the bit pattern to each of the plurality of cells of the random access memory.

### Claim 4 (depends on 2)

The apparatus of claim 2 further comprising:
means for selecting the memory for read access or write access; and
a multiplexor for selecting the plurality of interrupt lines to form the specific address in the latch means during the read access to the random access memory, and for selecting a plurality of address lines to form the specific address in the latch means during the write access of the random access memory.

### Claim 5

A method for muting interrupt signals in a computer system, comprising:
receiving, from interrupt sources, interrupt signals on a plurality of interrupt lines;
forming an address of a random access memory from the interrupt signals received on the plurality of interrupt lines;
accessing the random access memory at the address formed by the interrupt signals; and
transmitting to an interrupt processor a bit pattern stored at the address of the random access memory selected by the address formed by the interrupt signals.