# US 5,708,800 A · High speed microprocessor for processing and transferring N-bits of M-bit data

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- Number: US 5,708,800 A
- Document ID: US5708800A
- Status: Granted
- Kind: A
- Application number: 08/487,170
- Filed: 1995-06-07
- Granted: 1998-01-13
- Earliest claimed: 1994-09-27
- Assignees: Mitsubishi Denki Kabushiki Kaisha; Mitsubishi Electric Semiconductor Software Co., Ltd.
- Inventors: Hiroshi Tateishi; Hiroki Takahashi; Kazuo Nakamura
- Web page: https://patentgrep.com/patent/US5708800A

## CPC

- G06F 5/00: Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor.

## Claims

### Claim 1

A microprocessor for transferring N bits of a M-bit data stored in a first register of a microprocessor to an arbitrary M-bit data area of an external memory, where N and M are positive integers and N<M, comprising:
a) a control circuit for generating control signals to control an operation of the microprocessor;
b) a register group including at least the first register and a second register;
c) a first operand bus and a second operand bus coupled to said register group;
d) an ALU connected to the first and second operand buses and carrying out a first operation on the M-bit data inputted from first register via the first operand bus;
e) a destination bus coupled to the ALU and the second register, the ALU outputting a first operation result to the second register via the destination bus;
f) a mask ROM connected to the first and second operand buses and generating a predetermined mask data for masking M-N or N bits of the M-bit data and outputting the predetermined mask data to the ALU via the first or second operand bus, said ALU carrying out a second operation between the first operation result stored in the second register and the predetermined mask data, and outputting a second operation result which is stored in said second register via the destination bus; and
g) a memory data register connected to the first and second operand buses and the destination bus, and receiving M-bit data from the external memory and outputting the M-bit data to said ALU via the first or second operand bus, said ALU carrying out a third operation between the M-bit data and the predetermined mask data, and outputting a third operation result to the destination bus.

### Claim 2 (depends on 1)

The microprocessor of claim 1, wherein N equals 4 and M equals 8.

### Claim 3 (depends on 2)

The microprocessor of claim 2, wherein the predetermined mask data used for masking the first operation result during the second operation of said ALU is 0F (hexadecimal), and the predetermined mask data for masking the M-bit data from said memory data register during the third operation of said ALU is F0 (hexadecimal).

### Claim 4 (depends on 2)

The microprocessor of claim 2, wherein the predetermined mask data used for masking the first operation result during the second operation of said ALU is F0 (hexadecimal), and the predetermined mask data for masking the M-bit data from said memory data register during the third operation of said ALU is 0F.

### Claim 5 (depends on 1)

The microprocessor of claim 1, wherein the microprocessor transfers N high-order bits of the M-bit data stored in the first register to N low-order bits of the arbitrary M-bit data area of the external memory.

### Claim 6 (depends on 1)

The microprocessor of claim 1, wherein the microprocessor transfers N low-order bits of the M-bit data stored in the first register to N high-order bits of the arbitrary M-bit data area of the external memory.

### Claim 7 (depends on 1)

The microprocessor of claim 1, wherein said ALU shifts by one bit the M-bit data from the first register and said ALU shifts by one bit at least N-1 times the first operation result temporarily stored in said second register.

### Claim 8 (depends on 1)

The microprocessor of claim 1, wherein the second and third operations are logical AND operations.

### Claim 9 (depends on 1)

The microprocessor of claim 1, wherein said control circuit includes:
i) a decode circuit to retrieve and to decode an instruction from the external memory, and
ii) a ROM or random logic having a microprogram to generate an input/output control signal, a register select signal, an operation control signal and a data selection signal in accordance with the decoded instruction from said decode circuit.

### Claim 10 (depends on 1)

The microprocessor of claim 1, wherein the third operation result is stored in said memory data register, and said second operation result stored in said second register and said third operation result stored in said memory data register are inputted to said ALU which carries out a fourth operation to output a fourth operation result to said memory data register, and said fourth operation result being transferred from said memory data register to the external memory.

### Claim 11 (depends on 10)

The microprocessor of claim 10, wherein the fourth operation is a logical OR operation of the second and third operation results.

### Claim 12

A microprocessor for transferring N bits of a M-bit data stored in a first register of a microprocessor to an arbitrary M-bit data area of an external memory, where N and M are positive integers and N<M, comprising:
a control circuit for generating control signals to control an operation of the microprocessor;
a second register;
a first operand bus and a second operand bus coupled to said first register and said second register;
a mask ROM connected to the first and second operand buses and generating a predetermined mask data for masking M-N or N bits of data;
an ALU connected to the first and second operand buses and carrying out a first operation on the M-bit data inputted from first register and the predetermined mask data and outputting a first operation result, the first operation result being temporarily stored in the second register; and
a memory data register connected to the first and second operand buses and the destination bus, and receiving M-bit data from the external memory and outputting the M-bit data to said ALU via the first or second operand bus, said ALU carrying out a second operation between the M-bit data and the predetermined mask data, and outputting a second operation result to the destination bus.

### Claim 13 (depends on 12)

The microprocessor of claim 12, wherein N equals 4 and M equals 8.

### Claim 14 (depends on 13)

The microprocessor of claim 13, wherein the predetermined mask data used for masking the M-bit data of the first register during the first operation of said ALU is F0 (hexadecimal), and the predetermined mask data for masking the M-bit data from said memory data register during the second operation of said ALU is 0F (hexadecimal).

### Claim 15 (depends on 13)

The microprocessor of claim 13, wherein the predetermined mask data used for masking the M-bit data from the first register during the first operation of said ALU is 0F (hexadecimal), and the predetermined mask data for masking the M-bit data from said memory data register during the second operation of said ALU is F0.

### Claim 16 (depends on 12)

The microprocessor of claim 12, wherein the microprocessor transfers N high-order bits of the M-bit data stored in the first register to N high-order bits of the arbitrary M-bit data area of the external memory.

### Claim 17 (depends on 12)

The microprocessor of claim 12, wherein the microprocessor transfers N low-order bits of the M-bit data stored in the first register to N low-order bits of the arbitrary M-bit data area of the external memory.

### Claim 18 (depends on 12)

The microprocessor of claim 12, wherein the first and second operations are logical AND operations.

### Claim 19 (depends on 12)

The microprocessor of claim 12, wherein said control circuit includes:
i) a decode circuit to retrieve and to decode an instruction from the external memory, and
ii) a ROM or random logic having a microprogram to generate an input/output control signal, a register select signal, an operation control signal and a data selection signal in accordance with the decoded instruction from said decode circuit.

### Claim 20 (depends on 12)

The microprocessor of claim 12, wherein the second operation result is stored in said memory data register, and said first operation result stored in said second register and said second operation result stored in said memory data register are inputted to said ALU which carries out a third operation to output a third operation result to said memory data register, and said third operation result being transferred from said memory data register to the external memory.

### Claim 21 (depends on 20)

The microprocessor of claim 20, wherein the third operation is a logical OR operation of the first and second operation results.

### Claim 22

A method of transferring N bits of a M-bit data stored in a first register of a microprocessor to an arbitrary M-bit data area of an external memory, where N and M are positive integers and N<M, comprising the steps of:
retrieving and decoding an instruction from the external memory;
performing a first logical operation on the M-bit data inputted from first register into an arithmetic logic unit (ALU) to generate a first operation result;
outputting the first operation result via a destination bus and temporarily storing the first operation unit result in a second register, a first operand bus and a second operand bus each being coupled to said first and second registers and the ALU;
generating a predetermined mask data stored in a mask ROM and outputting the predetermined mask data from the mask ROM to the ALU, the mask ROM being connected to the first and second operand bus and transferring the mask data from the mask ROM to the ALU via the first or second operand bus;
performing a second logical operation between the first operation result stored in the second register and the predetermined mask data from the mask ROM inputted to the ALU and outputting a second operation result on the destination bus;
storing the second operation result in the second register;
transferring M-bit data from the external memory to a memory data register connected to the first and second operand buses and the destination bus; and
performing a third logical operation between the M-bit data from the memory data register and the predetermined mask data from the mask ROM inputted to the ALU, and outputting a third operation result to the destination bus.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
i) storing the third operation result in the memory data register;
j) performing a fourth logical operation between the second operation result from the second register and the third operation result from the memory data register inputted into the ALU to generate a fourth operation result; and
k) transferring the fourth operation result to the external memory.

### Claim 24 (depends on 22)

The method of claim 22, wherein the second and third operations are logical AND operations.

### Claim 25 (depends on 23)

The method of claim 23, wherein the fourth operation is a logical OR operation of the second and third operation results.

### Claim 26

A method of transferring N bits of a M-bit data stored in a first register of a microprocessor to an arbitrary M-bit data area of an external memory, where N and M are positive integers and N<M, comprising the steps of:
retrieving and decoding an instruction from the external memory;
generating a predetermined mask data stored in a mask ROM and outputting the predetermined mask data from the mask ROM to an arithmetic logic unit (ALU);
performing a first logical operation on the M-bit data from the first register and the predetermined mask data from the mask ROM inputted into the ALU to generate a first operation result;
outputting the first operation result via a destination bus and temporarily storing the first operation unit result in a second register, a first operand bus and a second operand bus each being coupled to said first and second registers, the mask ROM and the ALU with the mask ROM transferring the mask data from the mask ROM to the ALU via the first or second operand bus; and
performing a second logical operation between the M-bit data from the memory data register and the predetermined mask data from the mask ROM inputted to the ALU to generate a second operation result which is stored in the memory data register via the destination bus.

### Claim 27 (depends on 26)

The method of claim 26 further comprising:
g) performing a third logical operation between the first operation result from the second register and the second operation result from the memory data register inputted into the ALU to generate a third operation result; and
h) transferring the third operation result to the external memory.

### Claim 28 (depends on 27)

The method of claim 27, wherein the third operation is a logical OR operation of the first and second operation results.

### Claim 29 (depends on 26)

The method of claim 26, wherein the first and second operations are logical AND operations.