# US 5,708,797 A · IC memory with divisional memory portions

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- Number: US 5,708,797 A
- Document ID: US5708797A
- Status: Granted
- Kind: A
- Application number: 08/586,375
- Filed: 1996-01-17
- Granted: 1998-01-13
- Earliest claimed: 1995-01-28
- Assignees: Sony Corporation
- Inventors: Yuji Kobayashi
- Web page: https://patentgrep.com/patent/US5708797A

## CPC

- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An IC (integrated circuit) memory is made by using a chip of a minimum size that can accommodate memory of a desired capacity. Specifically, the chip has the size of (6.33.times.6.34) mm.sup.2, and its effective chip size is (4.33.times.4.43) mm.sup.2 1-port RAM (random access memory) 1 of 792w (word length).times.24 bits (bit width), 1-port RAM 2 of 220w.times.24 bits, and a logic circuit having about 3,000 gates for controlling these RAMs are provided in the effective chip size.

## Claims

### Claim 1

An IC memory having a capacity determined by a word length and a bit width of data to be stored therein, said IC memory comprising:
a chip having an effective chip size defined by a length L1 in a first direction and a length L2 in a second direction; and
a first memory portion and a second memory portion disposed on said chip, said first memory portion having a first word length portion not larger than said length L1 and having said bit width extending in said second direction, said second memory portion having said bit width extending in said first direction and having a second word length portion extending in said second direction, wherein
a sum of said bit width and said second word length portion is less than said length L2, and
a sum of said first word length portion and said second word length portion is substantially equal to said word length of said data to be stored.

### Claim 2 (depends on 1)

The IC memory according to claim 1, further comprising means for providing a delaying IC.

### Claim 3 (depends on 2)

The IC memory according to claim 2, wherein said length L1 is substantially equal to said length L2.

### Claim 4 (depends on 3)

The IC memory according to claim 3, further comprising
switching means connected at data input and output portions of said IC memory, and
control means for controlling generation of addresses of said first and second memory portions, and for controlling writing and reading on and from said first and second memory portions.

### Claim 5

An IC memory having a capacity determined by a word length and a bit width of data to be stored therein, said IC memory comprising:
a chip having an effective area less than an actual area of said chip; and
a plurality of memory portions each having a size in accordance with an allocated one of a plurality of regions in said effective area of said chip, wherein
said chip having a substantially square shape,
said plurality of memory portions has respective word length portions, and
a sum of said respective word length portions is substantially equal to said word length of said data to be stored.

### Claim 6 (depends on 5)

The IC memory according to claim 5, wherein said plurality of memory portions have said capacity as a whole such that a data writing/reading operation of said IC memory proceeds continuously.