# US 5,708,791 A · System and method for detecting the DRAM architecture in a computer

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- Number: US 5,708,791 A
- Document ID: US5708791A
- Status: Granted
- Kind: A
- Application number: 08/595,606
- Filed: 1996-02-02
- Granted: 1998-01-13
- Earliest claimed: 1996-02-02
- Assignees: National Semiconductor Corporation
- Inventors: Ian E. Davis
- Web page: https://patentgrep.com/patent/US5708791A

## CPC

- G06F 11/2289: {by configuration test}
- G06F 12/0684: {with feedback, e.g. presence or absence of unit detected by addressing, overflow detection}
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system and method cause the computer to automatically detect whether the computer implements a DRAM, and, if so, the architecture of the DRAM. More particularly, the system and method determine the requisite READ protocol for implementing the DRAM, and thus determine whether the DRAM implements a fast page (FP) architecture, an extended data out (EDO) architecture, or a burst extended data out (BEDO) architecture, since each architecture implements a unique READ protocol. From the analysis, the system and method determine if the DRAM is faulty, nonexistent, or of an unknown type. If the DRAM is faulty or of an unknown type, the system and method disable the DRAM.

## Claims

### Claim 1

A method of determining an architecture of a dynamic random access memory (DRAM) bank from a set of architectures including fast page (FP) architecture, extended data out (EDO) architecture, and burst extended data out (BEDO) architecture, comprising the steps of:
selecting a DRAM bank to examine;
writing a first predetermined word to a first memory location in the DRAM bank, and a second predetermined word to a second memory location which is sequential to the first memory location;
reading from the first and separately reading from the second memory locations to obtain a first read word and a second read word respectively; and
comparing the second read word with the first predetermined word, and if the second read word matches the first predetermined word, then indicating that the architecture of the selected DRAM bank is a BEDO architecture.

### Claim 2 (depends on 1)

The method recited in claim 1, wherein the step of comparing the second read word with the first predetermined word further comprises the step of comparing the second read word with the second predetermined word, and if the second read word equals the second predetermined word, then concluding that the architecture of the DRAM bank is an architecture from the group consisting of FP and EDO architectures.

### Claim 3 (depends on 2)

The method recited in claim 2 further comprising, after the step of comparing, the step of disabling the DRAM bank if the second read word is different from the first and the second predetermined words.

### Claim 4 (depends on 2)

The method recited in claim 2 wherein the DRAM bank has a data output line, and further comprising the steps of, if the DRAM bank architecture is one of the FP and EDO architectures, then:
forcing the data output line to a first logic level when the DRAM bank stops driving data signals at a second logic level to the data output line; and
examining the logic level of the data output line, and if the logic level is at the first logic level, then concluding that the DRAM bank architecture is an FP architecture, and if the logic level is at the second logic level, then concluding that the DRAM bank architecture is an EDO architecture.

### Claim 5 (depends on 4)

The method recited in claim 4, wherein the step of forcing the data output line uses a pull-down resistor to force the output line to a low first logic level.

### Claim 6 (depends on 4)

The method recited in claim 4, wherein the step of forcing the data output line uses a pull-up resistor to force the output line to a high first logic level.

### Claim 7 (depends on 4)

The method recited in claim 4, further comprising the step of de-asserting a column address strobe (CAS) signal a time interval sufficient to permit electrical discharge of a test signal before the step of examining the logic level; the time interval being established by taking the worst case capacitive load due to devices on a given DRAM data line multiplied by the resistance of a pull-up/pull-down resistor in the equation t=-RC*ln(Vfinal/Vinitial), where Vfinal/Vinitial is typically 0.2.

### Claim 8 (depends on 1)

The method recited in claim 1, wherein the step of writing includes writing third and fourth predetermined words to third and fourth sequential memory locations.

### Claim 9 (depends on 1)

The method recited in claim 1 wherein the step of reading is an FP-type READ operation.

### Claim 10

A system for determining an architecture of a dynamic random access memory (DRAM) bank from a set of architectures including fast page (FP) architecture, extended data out (EDO) architecture, and burst extended data out (BEDO) architecture, comprising:
test data writing means for writing first and second predetermined words respectively to first and second locations in the DRAM;
reading means for reading a first and separately reading a second read word respectively from the first and second locations in the DRAM; and
comparator means for comparing the second read word with the first predetermined word, and if the second read word matches the first predetermined word, then indicating that the DRAM bank architecture is a BEDO architecture.

### Claim 11 (depends on 10)

The system recited in claim 10, wherein the comparator means further compares the second read word with the second predetermined word, and if the second read word matches the second predetermined word, then indicates that the DRAM bank architecture is one from the set of FP and EDO architectures.

### Claim 12 (depends on 11)

The system recited in claim 11, further comprising disabling circuit means for disabling the DRAM bank if the second read word is different from the first and second predetermined words.

### Claim 13 (depends on 11)

The system recited in claim 11, further comprising a DRAM bank data output line, and logic level forcing means coupled to the data output line for forcing the logic level of the data output line to a first logic level when the DRAM bank stops driving data signals to the data output line.

### Claim 14 (depends on 13)

The system recited in claim 13, further comprising address assertion means for asserting a row address strobe (RAS) signal and a column address strobe (CAS) signal while a write enable (WE) signal is de-asserted to the DRAM bank to read from a preselected location in the DRAM bank.

### Claim 15 (depends on 14)

The system recited in claim 14, wherein the preselected location in the DRAM includes a plurality of bit storage locations, and stores data at a second logic level, different than the first logic level, at a bit storage location connected to the data output line.

### Claim 16 (depends on 15)

The system recited in claim 15, wherein the address assertion means is also the CAS de-assertion signal means.

### Claim 17 (depends on 16)

The system recited in claim 16, wherein if the DRAM bank has an FP architecture, then when the CAS signal is de-asserted, the DRAM bank stops driving data to the data output line, which is therefore forced by the logic level forcing means to the first logic level.

### Claim 18 (depends on 16)

The system recited in claim 16, wherein if the DRAM bank has an EDO architecture, then when the CAS signal is de-asserted, the DRAM bank continues driving data to the data output line, which therefore remains at the second logic level.

### Claim 19 (depends on 15)

The system recited in claim 15, wherein the logic level forcing means comprises a resistor coupled to the data output line.

### Claim 20 (depends on 19)

The system recited in claim 19, wherein the logic level forcing means takes into account the intrinsic capacitance of the DRAM, wiring, other devices on the DRAM data lines, and the resistor to determine a discharge time of the data output line.

### Claim 21 (depends on 20)

The system recited in claim 20, further comprising a comparator, and wherein the address assertion means also controls the de-assertion of the CAS signal, and after the discharge time the comparator samples the logic level of the data output line and compares the logic level of the data output line with the first and second logic levels.

### Claim 22 (depends on 15)

The system recited in claim 15, wherein the logic level forcing means comprises a pull-down resistor coupled to the data output line, and the first logic level is logic level low.

### Claim 23 (depends on 15)

The system recited in claim 15, wherein the logic level forcing means comprises a pull-up resistor coupled to the data output line, and the first logic level is logic level high.

### Claim 24

A program storage device having a computer program stored therein for causing a computer to perform the steps of:
selecting a dynamic random access memory (DRAM) bank to examine;
writing a first predetermined word to a first memory location in the DRAM bank, and a second predetermined word to a second memory location which is sequential to the first memory location;
reading from the first and separately reading from the second memory locations to obtain a first read word and a second read word respectively; and
comparing the second read word with the first predetermined word, and if the second read word is the same as the first predetermined word, then concluding that an architecture of the selected DRAM bank is a burst extended data out (BEDO) architecture.