# US 5,708,687 A · Synchronized clock using a non-pullable reference oscillator

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- Number: US 5,708,687 A
- Document ID: US5708687A
- Status: Granted
- Kind: A
- Application number: 08/674,422
- Filed: 1996-07-02
- Granted: 1998-01-13
- Earliest claimed: 1993-06-09
- Assignees: Alcatel Network Systems, Inc.
- Inventors: William E. Powell; Klaus-Hartwig Rieder; Gunter Horsch
- Web page: https://patentgrep.com/patent/US5708687A

## CPC

- H03L 7/1978: {using a cycle or pulse removing circuit}
- H03L 7/0994: {comprising an accumulator}
- H03L 7/1806: {the frequency divider comprising a phase accumulator generating the frequency divided signal}
- H03L 7/235: {Nested phase locked loops}
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H04L 7/0334: {Processing of samples having at least three levels, e.g. soft decisions}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

## Claims

### Claim 1

A method of synchronization, comprising the steps of:
comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
providing a stable reference frequency signal (40); and
providing (38) the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), wherein the step of providing the synthesized output signal comprises the steps of:
summing (120) the filtered error signal (36) and a phase accumulation modulation signal (122) for providing a summed signal (126) and a carry signal (128) with a superimposed phase jitter;
storing (124) the summed signal (126) for providing the phase accumulation modulation signal (122) in response to the stable reference frequency signal (40);
dividing (130) the carry signal (128) by an integer n for providing a divided signal (132);
comparing (136) the divided signal (132) and a divided feedback signal (138) for providing a second phase error signal (140);
filtering (142) the second phase error signal (140) for providing a filtered second phase error signal (144);
providing (146) the output signal (16) at a frequency according to the magnitude of the filtered second phase error signal (144); and
dividing (148) the output signal (16) for providing the divided feedback signal (138).

### Claim 2

A method of synchronization, comprising the steps of:
comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
providing a stable reference frequency signal (40); and
providing (38) the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), wherein the step of providing the synthesized output signal comprises the steps of:
summing (150) the filtered error signal (36) and a phase accumulation modulation signal (152) for providing a summed signal (156) and a carry signal (160) with superimposed phase jitter;
storing (154) the summed signal (156) for providing the phase accumulation modulation signal (152) in response to the stable reference frequency signal (40);
cycle stealing (158) a cycle in the stable reference signal (40) in response to the carry signal (160) for providing a gapped stable reference signal (162);
dividing (164) the gapped stable reference signal (162) for providing a divided signal (166);
comparing (172) the divided signal (166) and a divided feedback signal (179) for providing a phase error signal (173);
filtering (174) the phase error signal (173) for providing a filtered phase error signal (175);
providing (176) the output signal (16) at a frequency according to the magnitude of the filtered phase error signal (175); and
dividing (178) the output signal (16) for providing the divided feedback signal (179).

### Claim 3

A method of synchronization, comprising the steps of:
comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
providing a stable reference frequency signal (40); and
providing (38) the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), wherein the step of providing the frequency synthesized output signal comprises the steps of:
summing (186) the filtered error signal (36) and a phase accumulation modulation signal (189) for providing a summed signal (187) and a carry signal (191);
storing (188) the summed signal (187) for providing the phase accumulation modulation signal (189) in response to the stable reference frequency signal (40);
cycle stealing (190) a cycle in the stable reference signal (40) in response to the carry signal (191) for providing a gapped stable reference signal (192);
selecting (184) either the gapped stable reference signal (192) or the carry signal (191) in response to a selection signal (182) for providing the gapped stable reference signal (192) or the carry signal (191) for being divided (194) for providing a divided signal (196) with superimposed phase jitter;
comparing (198) the divided signal (196) and a divided feedback signal (200) for providing a second phase error signal (202);
filtering (204) the second phase error signal (202) for providing a filtered second phase error signal (206);
providing (208) the output signal (16) at a frequency according to the magnitude of the filtered second phase error signal (206); and
dividing (210) the output signal (16) for providing the divided feedback signal (200).

### Claim 4

Synchronizing apparatus, comprising:
means for comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
means for lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
means (40) for providing a stable reference frequency signal (40); and
means (38) for providing the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), wherein the means for providing the synthesized output signal (16) frequency comprises:
means for summing (120) the filtered error signal (36) and a phase accumulation modulation signal (122) for providing a summed signal (126) and a carry signal (128) with a superimposed phase jitter;
means for storing (124) the summed signal (126) for providing the phase accumulation modulation signal (122) in response to the stable reference frequency signal (40);
means for dividing (130) the carry signal (128) for providing a divided signal (132);
means for comparing (136) the divided signal (132) and a divided feedback signal (138) for providing a second phase error signal (140);
means for filtering (142) the second phase error signal (140) for providing a filtered second phase error signal (144);
means for providing (146) the output signal (16) at a frequency according to the magnitude of the filtered second phase error signal (144); and
means for dividing (148) the output signal (16) for providing the divided feedback signal (138).

### Claim 5

Synchronizing apparatus, comprising:
means for comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
means for lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
means (40) for providing a stable reference frequency signal (40); and
means (38) for providing the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), said means (38) for providing the frequency synthesized output signal comprising:
means for summing (150) the filtered error signal (36) and a phase accumulation modulation signal (152) for providing a summed signal (156) and a carry signal (160) with superimposed phase jitter;
means for storing (154) the summed signal (156) for providing the phase accumulation modulation signal (152) in response to the stable reference frequency signal (40);
means for cycle stealing (158) a cycle in the stable reference signal (40) in response to the carry signal (160) for providing a gapped stable reference signal (162);
means for dividing (164) the gapped stable reference signal (162) for providing a divided signal (166);
means for comparing (172) the divided signal (166) and a divided feedback signal (179) for providing a phase error signal (173);
means for filtering (174) the phase error signal (173) for providing a filtered phase error signal (175);
means for providing (176) the output signal (16) at a frequency according to the magnitude of the filtered phase error signal (175); and
means for dividing (178) the output signal (16) for providing the divided feedback signal (179).

### Claim 6

Synchronizing apparatus comprising:
means for comparing (14) a phase of a digital input signal (12) to a phase of a frequency synthesized output signal (16) for providing an error signal (18);
means for lowpass filtering (20) the error signal (18) for providing a filtered error signal (36);
means (40) for providing a stable reference frequency signal (40); and
means (38) for providing the frequency synthesized output signal (16) in response to the filtered error signal (36) and the stable reference signal (40), wherein the means (38) for providing the synthesized output signal frequency comprises:
means for summing (186) the filtered error signal (36) and a phase accumulation modulation signal (189) for providing a summed signal (187) and a carry signal (191);
means for storing (188) the summed signal (187) for providing the phase accumulation modulation signal (189) in response to the stable reference frequency signal (40);
means for cycle stealing (190) a cycle in the stable reference signal (40) in response to the carry signal (191) for providing a gapped stable reference signal (192);
means for selecting (184) either the gapped stable reference signal (192) or the carry signal (191) in response to a selection signal (182) for providing the gapped stable reference signal (192) or the carry signal (191) for being divided (194) for providing a divided signal (196) with superimposed phase jitter;
means for comparing (198) the divided signal (196) and a divided feedback signal (200) for providing a second phase error signal (202);
means for filtering (204) the second phase error signal (202) for providing a filtered second phase error signal (206);
means for providing (208) the output signal (16) at a frequency according to the magnitude of the filtered second phase error signal (206); and
means for dividing (210) the output signal (16) for providing the divided feedback signal (200).