# US 5,708,625 A · Voltage level detector > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,625 A - Document ID: US5708625A - Status: Granted - Kind: A - Application number: 08/415,512 - Filed: 1995-04-03 - Granted: 1998-01-13 - Earliest claimed: 1994-04-12 - Assignees: Fujitsu Limited - Inventors: Hajime Sato; Takaaki Furuyama - Web page: https://patentgrep.com/patent/US5708625A ## CPC - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A voltage level detector insusceptible to noise is disclosed. The voltage level detector includes a detector section, an output circuit section coupled to the detector section, and a delay circuit section provided between the detector section and the output circuit section. The detector section receives a target signal, and determines if the voltage level of the target signal lies within a predetermined voltage zone. The output circuit section outputs a detection signal when the target signal is found to be in the predetermined zone by the detector section. When the detector section detects that the target signal has come off the predetermined voltage zone, the delay circuit section delays the vanishing of the detection signal output from the output circuit section by a given delay time. ## Claims ### Claim 1 A voltage level detector including a first detector section having first and second transistors connected in series, a second detector section having third and fourth transistors connected in series, the first and second detector sections being arranged in parallel and connected to a power supply via a resistor, said voltage level detector comprising: a control terminal of said second transistor being supplied with a target signal whose voltage level is to be detected; a first delay circuit, connected to a control terminal of said first transistor, for inverting the level of said target signal and for allowing the inverted target signal to be supplied to said first transistor at a time later than the input of said target signal to said second transistor; a second delay circuit, connected to a control terminal of said third transistor, for allowing said target signal to be supplied to said third transistor at a time later than the input of the inverted target signal to said first transistor via said first delay circuit; and a third delay circuit, connected to a control terminal of said fourth transistor, for inverting the level of said target signal and for allowing the inverted target signal to be supplied to said fourth transistor at a time later than the input of the target signal to said second transistor and earlier than the input of the inverted target signal to said first transistor via said first delay circuit. ### Claim 2 (depends on 1) The voltage level detector according to claim 1, wherein said second delay circuit is provided with an input stage formed by an inverter whose threshold operating potential respecting said target signal is higher than a threshold operating potential of said second transistor; and wherein each of said first and third delay circuits is provided with an input stage formed by an inverter whose threshold operating potential respecting said target signal is higher than the threshold operating potential of the inverter of said second delay circuit. ### Claim 3 (depends on 1) The voltage level detector according to claim 1, wherein said first delay circuit is composed of the odd number of inverters; wherein said second delay circuit is composed of the even number of inverters; and wherein said third delay circuit is composed of the odd number of inverters. ### Claim 4 (depends on 1) The voltage level detector according to claim 1, wherein each of said first, second and third delay circuits is formed by at least one inverter. ### Claim 5 (depends on 2) The voltage level detector according to claim 2, wherein each of the inverters forming said input stages of said first, second and third delay circuits is formed by a pair of enhancement type P channel and N channel MOS transistors; and wherein the threshold operating potential of each of said inverters is adjusted by changing a ratio of the channel width of the enhancement type P channel MOS transistor to the channel width of the enhancement type N channel MOS transistor, or a ratio of the channel length of the enhancement type P channel MOS transistor to the channel length of the enhancement type N channel MOS transistor. ### Claim 6 (depends on 1) The voltage level detector according to claim 1, wherein each of said first to fourth transistors of said first and second detector sections is formed by an enhancement type N channel MOS transistor. ### Claim 7 (depends on 1) A semiconductor memory device including an address buffer for receiving an external address signal; an address change detector for detecting changes of the voltage level of the external address signal from the address buffer; and an address decoding circuit coupled to the address buffer and the address change detector for decoding the external address signal in response to an output from the address change detector, wherein said address change detector is formed by said voltage level detector according to claim 1. ### Claim 8 (depends on 1) A dynamic random access memory including an address buffer for receiving an external address signal; an address change detector for detecting changes of the voltage level of the external address signal from the address buffer; and an address decoding circuit coupled to the address buffer and the address change detector for decoding the external address signal in response to an output from the address change detector, wherein said address change detector is formed by said voltage level detector according to claim 1. ### Claim 9 A voltage level detector comprising: a flip-flop circuit including a first and second NAND gates and having a first and second input terminals, said first input terminal being supplied with a target signal whose voltage level is to be detected; a first inverter receiving said target signal and coupled to the second input terminal of said flip-flop circuit, said first inverter having a threshold operating potential lower than those of said first and second NAND gates; and a third NAND gate for receiving the outputs from said first and second NAND gates and for generating an output signal, said third NAND gate having a threshold operating potential lower than those of said first and second NAND gates. ### Claim 10 (depends on 9) The voltage level detector according to claim 9 further comprising a second inverter connected to an output terminal of said third NAND gate. ### Claim 11 (depends on 9) A semiconductor memory device including an address buffer for receiving an external address signal; an address change detector for detecting changes of the voltage level of the external address signal from the address buffer; and an address decoding circuit coupled to the address buffer and the address change detector for decoding the external address signal in response to an output from the address change detector, wherein said address change detector is formed by said voltage level detector according to claim 9. ### Claim 12 (depends on 9) A dynamic random access memory including an address buffer for receiving an external address signal; an address change detector for detecting changes of the voltage level of the external address signal from the address buffer; and an address decoding circuit coupled to the address buffer and the address change detector for decoding the external address signal in response to an output from the address change detector, wherein said address change detector is formed by said voltage level detector according to claim 9.