# US 5,708,624 A · Method and structure for controlling internal operations of a DRAM array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,624 A - Document ID: US5708624A - Status: Granted - Kind: A - Application number: 08/757,866 - Filed: 1996-11-27 - Granted: 1998-01-13 - Earliest claimed: 1996-11-27 - Assignees: Monolithic System Technology, Inc. - Inventors: Wingyu Leung - Web page: https://patentgrep.com/patent/US5708624A ## CPC - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method and structure for controlling the timing of an access to a DRAM array in response to a row access (RAS#) signal and the rising and/or falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a first transition of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before a second transition of the clock signal occurs. The second transition is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before a third transition of the clock signal. The third transition of the clock signal is then used to initiate the column address decoding operation of the DRAM array. In an alternative embodiment, the column address decoding is initiated when a column access (CAS#) signal is asserted and the clock signal undergoes the third transition. The first, second and third transitions can be consecutive or non-consecutive edges of the clock signal. A test mode is included which allows the DRAM array to be operated asynchronously for testing purposes. ## Claims ### Claim 1 A method of operating a dynamic random access memory (DRAM) array in response to a clock signal and an access control signal, the method comprising the steps of: asserting the access control signal to initiate an access to the DRAM array; initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating a sense amplifier equalization circuit of the DRAM array when the access control signal is asserted and the clock signal undergoes a first transition; and initiating a sense amplifier enabling operation when the access control signal is asserted and the clock signal undergoes a second transition. ### Claim 2 (depends on 1) The method of claim 1, further comprising the step of initiating a column address decoding operation when the access control signal is asserted and the clock signal undergoes a third transition. ### Claim 3 (depends on 1) The method of claim 1, further comprising the steps of: asserting a second access control signal; and initiating a column address decoding operation when the second access control signal is asserted and the clock signal undergoes a third transition. ### Claim 4 (depends on 1) The method of claim 1, wherein the step of deactivating the bit line equalization circuit comprises the steps of: transmitting an equalization signal to the gate of a first equalization transistor which extends across two bit lines of the DRAM array; and turning the first equalization transistor off in response to the equalization signal, thereby disconnecting the two bit lines. ### Claim 5 (depends on 4) The method of claim 4, wherein the step of deactivating the sense amplifier equalization circuit comprises the steps of: transmitting the equalization signal to the gate of a second equalization transistor which extends across two terminals of a sense amplifier of the DRAM array; and turning the second equalization transistor off in response to the equalization signal, thereby disconnecting the terminals of the sense amplifier. ### Claim 6 (depends on 1) The method of claim 1, wherein the row address decoding operation comprises the steps of: receiving a plurality of row address signals representative of a row address of the DRAM array; decoding the row address signals to determine the row address; and turning on a word line of the DRAM array which corresponds to the row address. ### Claim 7 (depends on 1) The method of claim 1, wherein the deactivation of the bit line equalization circuit is completed before the row address decoding operation is completed. ### Claim 8 (depends on 7) The method of claim 7, wherein the deactivation of the bit line equalization circuit and the row address decoding operation are completed before the clock signal undergoes the second transition. ### Claim 9 (depends on 1) The method of claim 1, wherein the sense amplifier enabling operation comprises the steps of: coupling a first input terminal of a sense amplifier to a first voltage supply; and coupling a second input terminal of the sense amplifier to a second voltage supply. ### Claim 10 (depends on 9) The method of claim 9, wherein the step of coupling a first input terminal of the sense amplifier to a first voltage supply, comprises the step of sequentially enabling a plurality of transistors connected in parallel between the first input terminal of the sense amplifier and the first voltage supply. ### Claim 11 (depends on 2) The method of claim 2, wherein the sense amplifier enabling operation is completed before the clock signal undergoes the third transition. ### Claim 12 (depends on 2) The method of claim 2, wherein the first, second and third transitions of the clock signal correspond to rising edges of the clock signal. ### Claim 13 (depends on 2) The method of claim 2, wherein the first, second and third transitions of the clock signal correspond to falling edges of the clock signal. ### Claim 14 (depends on 1) The method of claim 1, wherein the clock signal is generated by a phase locked loop circuit in response to a system clock signal. ### Claim 15 (depends on 14) The method of claim 14, wherein the system clock signal and the clock signal each have rising and falling edges, wherein the edges of the clock signal have a predetermined phase relationship with respect to the edges of the system clock signal. ### Claim 16 (depends on 1, 2) The method of claim 2, further comprising the steps of: providing a test signal having a first state and a second state; performing the steps recited in claims 1 and 2 when the test signal is in the first state; and initiating the row address decoding operation, deactivating the bit line equalization circuit, deactivating the sense amplifier equalization circuit, enabling the sense amplifier, and enabling the column address decoding operation in a self-timed manner, independent of the clock signal, when the test signal is in the second state. ### Claim 17 A method of operating a dynamic random access memory (DRAM) array in response to a clock signal and an access control signal, the method comprising the steps of: applying the clock signal and the access control signal to a synchronous state machine, wherein the synchronous state machine enters a first state and a second state in response to the clock signal when the access control signal is asserted; initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating a sense amplifier equalization circuit of the DRAM array when the state machine enters said first state for a first time; and initiating a sense amplifier enabling operation when the state machine enters said second state. ### Claim 18 (depends on 17) The method of claim 17, further comprising the step of initiating a column address decoding operation when the state machine enters said first state at time after the first time. ### Claim 19 (depends on 17) The method of claim 17, further comprising the steps of: asserting a second access control signal; and initiating a column address decoding operation when the second access control signal is asserted and the state machine enters said first state at a time after the first time. ### Claim 20 (depends on 17) The method of claim 17, wherein the state machine enters a different one of the first and second states at each rising edge of the clock signal when the access control signal is asserted. ### Claim 21 (depends on 17) The method of claim 17, wherein the state machine enters a different one of the first and second states at each falling edge of the clock signal when the access control signal is asserted. ### Claim 22 A control circuit for controlling a dynamic random access memory (DRAM) array having a plurality of bit line equalization circuits, a plurality of sense amplifiers, and a plurality of sense amplifier equalization circuits, the control circuit comprising: a clock input terminal for receiving a clock signal having a first state and a second state; an access control signal terminal for receiving an access control signal; a first signal generation circuit which generates an equalization signal when the access control signal is asserted and the clock signal undergoes a first transition, wherein the equalization signal disables the bit line equalization circuits and the sense amplifier equalization circuits; and a second signal generation circuit which generates a sense amplifier control signal when the access control signal is asserted and the clock signal undergoes a second transition, wherein the sense amplifier control signal enables the sense amplifiers. ### Claim 23 (depends on 22) The control circuit of claim 22, further comprising: a test input terminal for receiving a test signal; and a test circuit coupled to the test input terminal, wherein the test circuit is enabled when the test signal is asserted, and wherein the enabled test circuit decouples the clock signal from the first and second signal generation circuits, thereby allowing the first and second signal generation circuits to operate asynchronously in response to the access control signal. ### Claim 24 A method of operating a dynamic random access memory (DRAM) array, comprising the steps of: (a) providing a clock signal which transitions between a first state and a second state; (b) providing an access control signal, wherein the access control signal is asserted to initiate an access to the DRAM array; (c) initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating sense amplifier equalization circuit of the DRAM array when the access control signal is asserted and the clock signal undergoes a first transition; (d) initiating a sense amplifier enabling operation when the access control signal is asserted and the clock signal undergoes a second transition; (e) initiating a column address decoding operation when the access control signal is asserted and the clock signal undergoes a third transition; (f) providing a test signal having a first state and a second state; (g) performing steps (a)-(e) when the test signal is in the first state; and (h) initiating the row address decoding operation, deactivating the bit line equalization circuit, deactivating the sense amplifier equalization circuit, enabling the sense amplifier, and enabling the column address decoding operation in a self-timed manner, independent of the clock signal, when the test signal is in the second state. ### Claim 25 A method of operating a dynamic random access memory (DRAM) array, comprising the steps of: (a) providing a clock signal which transitions between a first state and a second state; (b) providing an access control signal, wherein the access control signal is asserted to initiate an access to the DRAM array; (c) initiating a row address decoding operation, deactivating a bit line equalization circuit of the DRAM array and deactivating sense amplifier equalization circuit of the DRAM array when the access control signal is asserted and the clock signal undergoes a first transition; (d) initiating a sense amplifier enabling operation when the access control signal is asserted and the clock signal undergoes a second transition; (e) initiating a column address decoding operation when a second access control signal is asserted and the clock signal undergoes a third transition; (f) providing a test signal having a first state and a second state; (g) performing steps (a)-(e) when the test signal is in the first state; and (h) initiating the row address decoding operation, deactivating the bit line equalization circuit, deactivating the sense amplifier equalization circuit, enabling the sense amplifier, and enabling the column address decoding operation in a self-timed manner, independent of the clock signal, when the test signal is in the second state.