# US 5,708,623 A · Semiconductor memory decoder device

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- Number: US 5,708,623 A
- Document ID: US5708623A
- Status: Granted
- Kind: A
- Application number: 08/735,655
- Filed: 1996-10-24
- Granted: 1998-01-13
- Earliest claimed: 1995-10-25
- Assignees: Hyundai Electronics Industries Co., Ltd.
- Inventors: Jae Myoung Choi
- Web page: https://patentgrep.com/patent/US5708623A

## CPC

- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device comprising a cell array including first and second cell array blocks for storing data therein, a first row address buffer for generating a first internal row address signal in response to an external row address signal and a first row address strobe signal, a second row address buffer for generating a second internal row address signal in response to the external row address signal and a second row address strobe signal, a first pre-decoder for pre-decoding the first internal row address signal from the first row address buffer, a second pre-decoder for pre-decoding the second internal row address signal from the second row address buffer, a first row decoder for selectively driving word lines in the first cell array block in response to the pre-decoded first internal row address signal from the first pre-decoder, and a second row decoder for selectively driving word lines in the second cell array block in response to the pre-decoded second internal row address signal from the second pre-decoder. The memory device further comprises a row address strobe bar buffer for generating the first and second row address strobe signals in response to an external row address strobe bar signal, a column address strobe bar signal, a write enable signal, an output enable signal and a mode enable signal.

## Claims

### Claim 1

A memory device comprising:
a cell array including first and second cell array blocks for storing data therein;
a first row address buffer for generating a first internal row address signal in response to an external row address signal and a first row address strobe signal;
a second row address buffer for generating a second internal row address signal in response to the external row address signal and a second row address strobe signal;
a first pre-decoder for pre-decoding the first internal row address signal from said first row address buffer;
a second pre-decoder for pre-decoding the second internal row address signal from said second row address buffer;
a first row decoder for selectively driving word lines in said first cell array block in response to the pre-decoded first internal row address signal from said first pre-decoder; and
a second row decoder for selectively driving word lines in said second cell array block in response to the pre-decoded second internal row address signal from said second pre-decoder.

### Claim 2 (depends on 1)

A memory device as set forth in claim 1, further comprising control means for generating the first and second row address strobe signals in response to an external row address strobe bar signal, a column address strobe bar signal, a write enable signal, an output enable signal and a mode enable signal and applying the generated first and second row address strobe signals to said first and second row address buffers, respectively.

### Claim 3 (depends on 1)

A memory device as set forth in claim 1, wherein said first and second row decoder, said first and second row address buffers and said first and second pre-decoders are alternately operated.

### Claim 4 (depends on 2)

A memory device as set forth in claim 2, wherein said first row address buffer includes a first internal row address generator for generating the first internal row address signal in response to the external row address signal and the first row address strobe signal from said control means.

### Claim 5 (depends on 4)

A memory device as set forth in claim 4, wherein said second row address buffer includes a second internal row address generator for generating the second internal row address signal in response to the external row address signal and the second row address strobe signal from said control means.