# US 5,708,617 A · Regressive drive sense amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,617 A - Document ID: US5708617A - Status: Granted - Kind: A - Application number: 08/790,377 - Filed: 1997-01-28 - Granted: 1998-01-13 - Earliest claimed: 1997-01-28 - Assignees: Micron Technology, Inc. - Inventors: Brian M. Shirley - Web page: https://patentgrep.com/patent/US5708617A ## CPC - G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} - G11C 7/065: {Differential amplifiers of latching type} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor. ## Claims ### Claim 1 A pull-down circuit in a sense amplifier having a common node and receiving a power supply voltage, the pull-down circuit comprising: a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground; a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor; a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage; and a regressive drive bias circuit coupled to the gate of the choke transistor and providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor. ### Claim 2 (depends on 1) The pull-down circuit of claim 1 wherein the regressive drive bias circuit comprises: a first-stage transistor tree including: a first N-channel transistor having a source coupled to ground, a gate, and a drain coupled to the gate and to a first node, and a first resistive element coupled between the power supply and the first node; and a second-stage transistor tree including: a first P-channel transistor having a source coupled to the power supply, a gate, and a drain coupled to the gate, a second P-channel transistor having a source coupled to the gate and drain of the first P-channel transistor, a gate coupled to the first node, and a drain coupled to the gate of the choke transistor, and a second resistive element coupled between ground and the drain of the second P-channel transistor. ### Claim 3 (depends on 2) The pull-down circuit of claim 2 wherein the first resistive element includes a third P-channel transistor having a source coupled to the power supply, a gate coupled to ground, and a drain coupled to the first node. ### Claim 4 (depends on 2) The pull-down circuit of claim 2 wherein the first resistive element includes a resistor coupled between the power supply and the first node. ### Claim 5 (depends on 2) The pull-down circuit of claim 2 wherein the second resistive element includes a second N-channel transistor having a source coupled to ground, a gate coupled to the power supply, and a drain coupled to the drain of the second P-channel transistor. ### Claim 6 (depends on 2) The pull-down circuit of claim 2 wherein the second resistive element includes a resistor coupled between ground and the drain of the second P-channel transistor. ### Claim 7 (depends on 1) The pull-down circuit of claim 1 wherein the pull-down gate control circuit is an inverter and the gate control signal represents an inverted form of the input signal. ### Claim 8 A pull-down circuit in a sense amplifier having a common node and receiving a power Supply voltage, the pull-down circuit comprising: a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground; a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor; a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage; a first-stage transistor tree including: a first N-channel transistor having a source coupled to ground, a gate, and a drain coupled to the gate and to a first node, and a first resistive element coupled between the power supply and the first node; and a second-stage transistor tree stage including: a first P-channel transistor having a source coupled to the power supply, a gate, and a drain coupled to the gate, and a second P-channel transistor having a source coupled to the gate and drain of the first p-channel transistor, a gate coupled to the first node, and a drain coupled to coupled to the gate of the choke transistor, and a second resistive element coupled between ground and the drain of the second P-channel transistor. ### Claim 9 (depends on 8) The pull-down circuit of claim 8 wherein the first resistive element includes a third P-channel transistor having a source coupled to the power supply, a gate coupled to ground, and a drain coupled to the first node. ### Claim 10 (depends on 8) The pull-down circuit of claim 8 wherein the first resistive element includes a resistor coupled between the power supply and the first node. ### Claim 11 (depends on 8) The pull-down circuit of claim 8 wherein the second resistive element includes a second N-channel transistor having a source coupled to ground, a gate coupled to the power supply, and a drain coupled to the drain of the second P-channel transistor. ### Claim 12 (depends on 8) The pull-down circuit of claim 8 wherein the second resistive element includes a resistor coupled between ground and the drain of the second P-channel transistor. ### Claim 13 (depends on 8) The pull-down circuit of claim 8 wherein the first-stage and second-stage transistor trees operate to provide a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor. ### Claim 14 A method of discharging a sense amplifier having a common node and receiving a power supply voltage, the method comprising the steps of: providing an input signal; providing a bias voltage based on the value of the power supply voltage, wherein a relatively low bias voltage is provided at relatively low power supply voltages and a relatively high bias voltage is provided at relatively high power supply voltages; regulating an input current based on the power supply voltage and the bias voltage to increase the input current at relatively low bias voltages and to decrease the input current at relatively high bias voltages; and discharging the sense amplifier based on the input signal and the input current. ### Claim 15 A method of controlling a pull-down circuit in a sense amplifier having a common node and receiving a power supply voltage, the pull-down circuit including a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground; a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor; and a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage, the method comprising the steps of: providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor; and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor. ### Claim 16 A sense amplifier comprising: a common node shared with other sense amplifiers; a pair of sense amplifier transistors having a cross-coupled gate and drain configuration to sense charge in a memory array and having sources coupled together and coupled to the common node; a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground; a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor; a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage; and a regressive drive bias circuit coupled to the gate of the choke transistor and providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor. ### Claim 17 A memory integrated circuit comprising: a memory array; a common node; a pair of sense amplifier transistors having a cross-coupled gate and drain configuration to sense charge in the memory array and having sources coupled together and coupled to the common node; a pull-down transistor having a drain coupled to the common node, a gate, and a source coupled to ground; a pull-down gate control circuit having a power terminal and receiving an input signal and providing a gate control signal based on the input signal to the gate of the pull-down transistor; a choke transistor having a drain coupled to the power terminal of the pull-down gate control circuit, a gate, and source coupled to the power supply voltage; and a regressive drive bias circuit coupled to the gate of the choke transistor and providing a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor, and providing a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.