# US 5,708,614 A · Data output control circuit of semiconductor memory device having pipeline structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,614 A - Document ID: US5708614A - Status: Granted - Kind: A - Application number: 08/784,783 - Filed: 1997-01-16 - Granted: 1998-01-13 - Earliest claimed: 1996-01-23 - Assignees: NEC Corporation - Inventors: Yasuji Koshikawa - Web page: https://patentgrep.com/patent/US5708614A ## CPC - G11C 29/14: Implementation of control logic, e.g. test mode decoders - G11C 29/38: Response verification devices - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G06F 2201/88: Monitoring involving counting - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In a method of testing a semiconductor memory device having a pipeline structure, a same data is stored in a plurality of memory cells in advance. The stored data are read out from the plurality of memory cells to produce data signals and amplified as the data signals. A determining section determines whether all the data signals are same, to generate a determination result signal. In accordance with the determination result signal, one of signals associated with the amplified data signals and predetermined signals are transferred to an output section in synchronous with a synchronous signal. The output section includes a plurality of output circuits each of which provides, as an indication signal, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to each of the transferred signals. Therefore, using at least one of the indication signals, whether the plurality of memory cells are correctly operable can be tested. ## Claims ### Claim 1 A semiconductor memory device having a pipeline structure, comprising: amplifier means for amplifying data signals from a plurality of data sources; determining means for determining whether all said data signals are same, to generate a determination result signal; synchronous signal generating means for generating a synchronous signal; transfer means for selectively transferring one of signals associated with said amplified data signals and predetermined signals in accordance with said determination result signal and in synchronous with said synchronous signal; and output means including a plurality of output circuits, for providing, for each of said data signals, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to the transferred signals such that same output signals are outputted from said plurality of output circuits. ### Claim 2 (depends on 1) A semiconductor memory device according to claim 1, wherein said transfer means includes: latching means for latching said amplified data signals in response to said synchronous signal to generate latched signals; and output control means for selectively transferring one of signals associated with said latched signals and said predetermined signals to said output means in accordance with said determination result signal. ### Claim 3 (depends on 2) A semiconductor memory device according to claim 2, wherein said output control means outputs the signals associated with said latched signals to said output means in accordance with said determination result signal when it is determined by said determining means that all said data signals are same and said output means outputs one of said high level signals and said low level signals based on the signals associated with said latched signals. ### Claim 4 (depends on 2) A semiconductor memory device according to claim 2, wherein said output control means outputs said predetermined signals to said output means in accordance with said determination result signal when it is determined by said determining means that all said data signals are not same and said output means outputs the signal indicative of said high impedance state. ### Claim 5 (depends on 2) A semiconductor memory device according to claim 2, wherein said determining means determines whether all said data signals are same, based on said amplified data signals to generate said determination result signal. ### Claim 6 (depends on 5) A semiconductor memory device according to claim 5, wherein said latching means latches said determination result signal in response to said synchronous signal to output the latched determination result signal to said output control means. ### Claim 7 (depends on 1) A semiconductor memory device according to claim 1, wherein said transfer means includes: latching means for latching said amplified data signals in response to said synchronous signal to generate latched signals; delay means for delaying said latched signals; and output control means for selectively transferring one of signals associated with said delated signals and said predetermined signals to said output means in accordance with said determination result signal. ### Claim 8 (depends on 7) A semiconductor memory device according to claim 7, wherein said output control means outputs the signals associated with the delayed signals to said output means in accordance with said determination result signal when it is determined by said determining means that all said data signals are same and said output means outputs one of said high level signals and said low level signals based on said latched signals. ### Claim 9 (depends on 7) A semiconductor memory device according to claim 7, wherein said output control means outputs said predetermined signals to said output means in accordance with said determination result signal when it is determined by said determining means that all said data signals are not same and said output means outputs the signal indicative of said high impedance state. ### Claim 10 (depends on 7) A semiconductor memory device according to claim 7, wherein said determining means determines whether all said data signals are same, based on said latched signals to generate said determination result signal. ### Claim 11 A method of testing a semiconductor memory device having a pipeline structure, comprising the steps of: storing same data in a plurality of memory cells; reading out the data from the plurality of memory cells to produce data signals and amplifying the data signals; determining whether all said data signals are same, to generate a determination result signal; selectively transferring one of signals associated with said amplified data signals and predetermined signals in accordance with said determination result signal in synchronous with a synchronous signal; providing, as an indication signal, one of a low level signal, a high level signal and a signal indicative of a high impedance state in response to each of the transferred signals; and judging whether the plurality of memory cells are correctly operable, using at least one of the indication signals. ### Claim 12 (depends on 11) A method according to claim 11, wherein said transferring step includes: latching said amplified data signals in response to said synchronous signal to generate latched signals; and selectively transferring one of signals associated with said latched signals and said predetermined signals in accordance with said determination result signal. ### Claim 13 (depends on 12) A method according to claim 12, wherein said selectively outputting step includes outputting said latched signals in accordance with said determination result signal when it is determined that all said signals are same, such that one of said high level signals and said low level signals is outputted based on said latched signals. ### Claim 14 (depends on 12) A method according to claim 12, wherein said selectively outputting step includes outputting said predetermined signals in accordance with said determination result signal when it is determined that all said data signals are not same, such that the signal indicative of said high impedance state is outputted. ### Claim 15 (depends on 12) A method according to claim 12, wherein said determining step includes determining whether all said data signals are same, based on said amplified data signals to generate said determination result signal. ### Claim 16 A method according to 15, wherein said latching step includes latching said determination result signal in response to said synchronous signal. ### Claim 17 (depends on 11) A method according to claim 11, wherein said transferring step includes: latching said amplified data signals in response to said synchronous signal to generate latched signals; delaying said latched signals; selectively transferring one of said latched signals and said predetermined signals in accordance with said determination result signal. ### Claim 18 (depends on 17) A method according to claim 17, wherein said selectively outputting step includes outputting the delayed signals in accordance with said determination result signal when it is determined that all said data signals are same, such that one of said high level signals and said low level signals is outputted based on said latched signals. ### Claim 19 A data output control circuit comprising: a plurality of data amplifiers receiving a plurality of data signals; a comparing circuit determining that all said data signals are same and outputting a determination signal indicating a coincidence or a non-coincidence; a synchronous signal generator generating a synchronous signal; a first synchronizing circuit and a plurality of second synchronizing circuits being commonly supplied with said synchronous signal, said first synchronizing circuit transferring said determination signal at timing of generating of said synchronous signal, said plurality of second synchronizing circuits transferring said plurality of data signals at timing of generating of said synchronous signal; and a plurality of output circuits receiving said determination signal from said first synchronizing circuit and said data signals from said second synchronizing circuits and outputting said plurality of data signals in response to said determination signal. ### Claim 20 (depends on 19) A data output control circuit according to claim 19, wherein said plurality of output circuits includes a plurality of output control circuits receiving said determination signal from said first synchronizing circuit and said data signals from said plurality of second synchronizing circuits and outputting a plurality of output signals indicating coincidence when said synchronous signal indicating said coincidence and outputting at least one of said plurality of output signals indicating non-incidence when said synchronous signal indicating said non-coincidence .