# US 5,708,611 A · Synchronous semiconductor memory device

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- Number: US 5,708,611 A
- Document ID: US5708611A
- Status: Granted
- Kind: A
- Application number: 08/801,889
- Filed: 1997-02-18
- Granted: 1998-01-13
- Earliest claimed: 1994-11-22
- Assignees: Mitsubishi Denki Kabushiki Kaisha
- Inventors: Hisashi Iwamoto; Yasuhiro Konishi
- Web page: https://patentgrep.com/patent/US5708611A

## CPC

- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.

## Claims

### Claim 1

A synchronous semiconductor memory device having a mode requiring an internal clock signal and a mode not requiring said internal clock signal, comprising:
a plurality of memory arrays including a plurality of memory cells arranged in a matrix,
an internal clock generation circuit for generating said internal clock signal in synchronization with an external clock signal,
a data input/output circuit for carrying out data input and output between a selected memory cell in said plurality of memory arrays and an external source in synchronization with said internal clock signal, and
a control circuit for inactivating said internal clock generation circuit for a predetermined time period in response to designation of said mode not requiring said internal clock signal.

### Claim 2 (depends on 1)

The synchronous semiconductor memory device according to claim 1, wherein said mode not requiring said internal clock signal includes an auto-refresh mode in which a memory array different from a previously refreshed memory array out of said plurality of memory arrays is refreshed.

### Claim 3 (depends on 1)

The synchronous semiconductor memory device according to claim 1, wherein said mode not requiring said internal clock signal comprises a self refresh mode in which said plurality of memory arrays are sequentially refreshed in said self refresh mode.

### Claim 4 (depends on 1)

The synchronous semiconductor memory device according to claim 1, wherein said mode not requiring said internal clock signal comprises an auto-refresh mode that refreshes a memory array different from a previously refreshed memory array out of said plurality of memory arrays, and
a self refresh mode that sequentially refreshes said plurality of memory arrays,
wherein said control circuit comprises
a first signal generation circuit for providing an auto refresh detection signal for only a predetermined time period according to specification of said auto-refresh mode by a control signal,
a second signal generation circuit for providing a self refresh detection signal during designation of a start of said self refresh mode to termination of that self refresh mode by said control signal, and
a gate circuit for inhibiting input of said external clock signal to said internal clock generation circuit according to one of said auto refresh detection signal and said self refresh signal from one of said first and second signal generation circuits,
said synchronous semiconductor memory device further comprises a refresh circuit for carrying out said auto-refresh mode according to said auto refresh detection signal from said first signal generation circuit, and carrying out said self refresh mode according to said self refresh detection signal from said second signal generation circuit.

### Claim 5 (depends on 3)

The synchronous semiconductor memory device according to claim 3,
wherein said control circuit comprises
a first signal generation circuit for providing a self refresh detection signal during designation of a start of said self refresh mode to designation of termination of that self refresh mode,
a first gate circuit for inhibiting input of said external clock signal to said internal clock generation circuit in response to said self refresh detection signal from said first signal generation circuit,
a second signal generation circuit for providing an activation signal at a predetermined period in response to said self refresh detection signal from said first signal generation circuit, and
a second gate circuit for providing said external clock signal to said internal clock generation circuit in response to said activation signal from said second signal generation circuit.