# US 5,708,606 A · Semiconductor memory device and high-voltage switching circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,606 A - Document ID: US5708606A - Status: Granted - Kind: A - Application number: 08/773,893 - Filed: 1997-01-17 - Granted: 1998-01-13 - Earliest claimed: 1994-08-19 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi - Web page: https://patentgrep.com/patent/US5708606A ## CPC - G11C 29/028: {with adaption or trimming of parameters} - G11C 16/12: Programming voltage switching circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/30: Power supply circuits - G11C 29/50: Marginal testing, e.g. race, voltage or current testing - G11C 29/50004: {of threshold voltage} - G11C 29/83: {with reduced power consumption} - G11C 16/04: using variable threshold transistors, e.g. FAMOS - G11C 2029/5004: {Voltage} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device comprises an array of electrically rewritable memory cells which are arranged in a matrix, erasing section for applying an erasing voltage to the memory cells to effect erasing, and writing section for applying a writing voltage to the memory cells to effect writing, wherein in the erasing section and writing section, either MOS transistors to which a voltage higher than the erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than the erasing voltage and writing voltage contain MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V. ## Claims ### Claim 1 A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; said erasing means and writing means comprising a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first NMOS transistor having a gate, a source, and a drain coupled to said input terminal, a second NMOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first NMOS transistor, and a third NMOS transistor having a gate, a source coupled to the source of said first NMOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein the gates of said first and second NMOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first NMOS transistor to said source of said second NMOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third NMOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode. ### Claim 2 (depends on 1) A semiconductor memory device according to claim 1, wherein each of said memory cells is composed of a charge storage layer and a control gate laminated together on a semiconductor layer and composed of a source and a drain at a surface of said semiconductor substrate. ### Claim 3 (depends on 2) A semiconductor memory device according to claim 2, further comprising an well region provided on the surface of said substrate so as to include said source and drain of said memory cell. ### Claim 4 (depends on 3) A semiconductor memory device according to claim 3, wherein said erasing voltage is applied to said well region and a low erasing voltage is applied to said control gate of said memory cell. ### Claim 5 (depends on 3) A semiconductor memory device according to claim 3, wherein said writing voltage applied to said control gate of said memory cell and a specific voltage based on data is applied to bit line connected to said memory cell. ### Claim 6 (depends on 1) A semiconductor memory device according to claim 1, wherein said first and second MOS transistors are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V. ### Claim 7 A semiconductor memory device comprising; an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; said erasing means and writing means comprising a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first MOS transistor having a gate, a source, and a drain coupled to said input terminal, a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode. ### Claim 8 (depends on 7) A semiconductor memory device according to claim 7, wherein each of said memory cells is composed or a charge storage layer and a control gate laminated together on a semiconductor layer and composed of a source and a drain at a surface of said semiconductor substrate. ### Claim 9 (depends on 7) A semiconductor memory device according to claim 7, wherein said first MOS transistor and is an n-channel MOS transistor and is in a cut-off state under the condition at a voltage transferred to the source of said third MOS transistor with the substrate bias voltage at 0 V and the gate voltage at a predetermined second voltage and the drain voltage at said predetermined first voltage is applied to the source with the substrate bias voltage and gate voltage at 0 V. ### Claim 10 (depends on 7) A semiconductor memory device according to claim 7, wherein said first and second MOS transistors are n-channel MOS transistors and are in an inversion state under the conditions that the substrate bias voltage is at 0 V and the source voltage is said erasing voltage and writing voltage and that the gate voltage is said erasing voltage and said writing voltage added with a power-supply voltage. ### Claim 11 (depends on 7) A semiconductor memory device according to claim 7, wherein said first and second MOS transistors are n-channel MOS transistors and are in a cut-off state under the conditions that a voltage transferred to the source of said third MOS transistor with the substrate bias voltage at 0 V and the gate voltage at a predetermined second voltage and the drain voltage at said predetermined first voltage is applied to the source with the substrate bias voltage and gate voltage at 0 V, and are in an inversion state under the conditions that the substrate bias voltage is at 0 V and the source voltage is said erasing voltage and writing voltage and that the gate voltage is said erasing voltage and said writing voltage added with a power-supply voltage. ### Claim 12 (depends on 7) A semiconductor memory device according to claim 7, wherein said first and second MOS transistors are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V. ### Claim 13 A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; said erasing means and writing means comprising a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first MOS transistor having a gate, a source, and a drain coupled to said input terminal, a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode said first, second and third MOS transistors composed of two types of MOS transistors, a first type and a second type, the second-type MOS transistor being an n-channel MOS transistor that is in an inversion state with the substrate bias voltage at 0 V and the gate and source voltages at a predetermined third voltage and in a cut-off state with the substrate bias voltage and gate voltage at 0 V and the source voltage at a predetermined fourth voltage, and the first-type MOS transistor being an n-channel MOS transistor that is in a weak inversion state or an inversion state with the substrate bias voltage, gate voltage, and source voltage at 0 V and having a threshold voltage higher than that of said second-type n-channel MOS transistor. ### Claim 14 (depends on 13) A semiconductor memory device according to claim 13, wherein each of said memory cells is composed of a charge storage layer and a control gate laminated together on a semiconductor layer and composed of a source and a drain at a surface of said semiconductor substrate. ### Claim 15 (depends on 13) A semiconductor memory device according to claim 13, wherein said first MOS transistor is an n-channel MOS transistor and is in a cut-off state under the condition at a voltage transferred to the source of said third MOS transistor with the substrate bias voltage at 0 V and the gate voltages at a predetermined second voltage and the drain voltage at said predetermined first voltage is applied to the source with the substrate bias voltage and gate voltage at 0 V. ### Claim 16 (depends on 13) A semiconductor memory device according to claim 13, wherein said first-type n-channel MOS transistors are in an inversion state under the conditions that the substrate bias voltage is at 0 V and the source voltage is said erasing voltage and writing voltage and that the gate voltage is said erasing voltage and said writing voltage added with a power-supply voltage. ### Claim 17 (depends on 13) A semiconductor memory device according to claim 13, wherein said first-type n-channel MOS transistors are in a cut-off state under the conditions that a voltage transferred to the source of said third MOS transistor with the substrate bias voltage at 0 V and the gate voltage at a predetermined second voltage and the drain voltage at said predetermined first voltage is applied to the source with the substrate bias voltage and gate voltage at 0 V, and are in an inversion state under the conditions that the substrate bias voltage is at 0 V and the source voltage is said erasing voltage and writing voltage and that the gate voltage is said erasing voltage and said writing voltage added with a power-supply voltage. ### Claim 18 A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; said erasing means and writing means comprising one of MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied and MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage and containing MOS transistors which are in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage 0 V. ### Claim 19 (depends on 18) A semiconductor memory device according to claim 18, wherein said erasing means and writing means comprise a high voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first NMOS transistor having a gate, a source, and a drain coupled to said input terminal, a second NMOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first NMOS transistor, and a third NMOS transistor having a gate, a source coupled to the source of said first NMOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein the gates of said first and second NMOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first NMOS transistor to said source of said second NMOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third NMOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode. ### Claim 20 A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; and said erasing means and writing means comprising either MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage composed only of MOS transistors of a first type, said MOS transistors being in a weak inversion state or an inversion state with their substrate bias voltage, gate voltage and source voltage at 0 V. ### Claim 21 (depends on 20) A semiconductor memory device according to claim 20, wherein: said erasing means and writing means comprise a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first MOS transistor having a gate, a source, and a drain coupled to said input terminal, a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode. ### Claim 22 A semiconductor memory device comprising: an array of electrically rewritable memory cells which are arranged in a matrix; erasing means for applying an erasing voltage to said memory cells to effect erasing; and writing means for applying a writing voltage to said memory cells to effect writing; and said erasing means and writing means comprising either MOS transistors to which a voltage higher than said erasing voltage and writing voltage is applied or MOS transistors which transfer a voltage higher than said erasing voltage and writing voltage being composed of two types of MOS transistors, a first type and a second type, the second-type MOS transistor being an n-channel MOS transistor that is in an inversion state with the substrate bias voltage at 0 V and the gate and source voltages at a power-supply voltage and in a cut-off state with the substrate bias voltage and gate voltage at 0 V and the source voltage at the power-supply voltage, and the first-type MOS transistor being an n-channel MOS transistor that is in a weak inversion state or an inversion state with the substrate bias voltage, gate voltage, and source voltage at 0 V and having a threshold voltage higher than that of said second-type n-channel MOS transistor. ### Claim 23 (depends on 22) A semiconductor memory device according to claim 22, wherein said erasing means and writing means comprise a high-voltage switching circuit for outputting a high voltage applied to an input terminal to an output terminal in a selected mode and electrically disconnecting said input terminal from said output terminal in the unselected mode, said high-voltage switching circuit comprising, a first MOS transistor having a gate, a source, and a drain coupled to said input terminal, a second MOS transistor having a gate, a source coupled to said output terminal, and a drain coupled to the source of said first MOS transistor, and a third MOS transistor having a gate, a source coupled to the source of said first MOS transistor, and a drain to which a predetermined first voltage is applied at least in the unselected mode, wherein said first, second and third MOS transistors are of the same conductivity type, the gates of said first and second MOS transistors are coupled to an ON voltage to transfer said high voltage applied via said input terminal to said drain of said first MOS transistor to said source of said second MOS transistor in the selected mode, and are grounded in the unselected mode, and the gate of said third MOS transistor is grounded in the selected mode and is coupled to a predetermined second voltage in the unselected mode said first, second and third MOS transistors composed of two types of MOS transistors, a first type and a second type, the second-type MOS transistor being an n-channel MOS transistor that is in an inversion state with the substrate bias voltage at 0 V and the gate and source voltages at a predetermined third voltage and in a cut-off state with the substrate bias voltage and gate voltage at 0 V and the source voltage at a predetermined fourth voltage, and the first-type MOS transistor being an n-channel MOS transistor that is in a weak inversion state or an inversion state with the substrate bias voltage, gate voltage, and source voltage at 0 V and having a threshold voltage higher than that of said second-type n-channel MOS transistor.