# US 5,708,597 A · Structure and method for implementing a memory system having a plurality of memory blocks

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- Number: US 5,708,597 A
- Document ID: US5708597A
- Status: Granted
- Kind: A
- Application number: 08/752,868
- Filed: 1996-11-20
- Granted: 1998-01-13
- Earliest claimed: 1996-11-20
- Assignees: Xilinx, Inc.
- Inventors: Steven H. Kelem
- Web page: https://patentgrep.com/patent/US5708597A

## CPC

- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system and method which allows a plurality of memory circuits to be operated independently as separate memories, or jointly as a single memory. Alternatively, the selected memory circuits are operated jointly and other memory circuits are operated independently. The configuration of the memory system can be varied dynamically during operation of the memory system.

## Claims

### Claim 1

A memory system comprising:
a first line set for receiving a first plurality of memory control signals;
a second line set for receiving a second plurality of memory control signals;
a first control line for receiving a split control signal having a first state and a second state;
a first switching logic circuit coupled to the first line set, the second line set and the first control line;
a first memory circuit;
a second memory circuit;
a third line set coupled between the first switching logic circuit and the first memory circuit; and
a fourth line set coupled between the first switching logic circuit and the second memory circuit, wherein the first switching logic couples the first line set to the third line set when the split signal is in the first state, thereby routing the first memory control signals to the first memory circuit, and couples the second line set to the fourth line set, thereby routing the second memory control signals to the second memory circuit, and wherein the first switching logic circuit couples one of the first and second line sets to the third and fourth line sets when the split signal is in the second state.

### Claim 2 (depends on 1)

The memory system of claim 1, further comprising a second control line for receiving a control signal having a first state and a second state, the second control line being coupled to the first switching logic circuit, wherein when the split signal is in the second state, the first switching logic circuit couples the first line set to the third and fourth line sets when the control signal is in the first state, and the first switching logic circuit couples the second line set to the third and fourth line sets when the control signal is in the second state.

### Claim 3 (depends on 1)

The memory system of claim 1, further comprising:
a second switching logic circuit coupled to receive a first output signal from the first memory circuit, a second output signal from the second memory circuit, and the split signal from the first control line, the second switching logic circuit routing the first and second output signals separately when the split signal is in the first state, the second switching logic circuit routing a selected one of the first and second output signals when the split signal is in the second state.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the second switching logic circuit is further coupled to selected lines of the first and second line sets, the signals on the selected lines identifying the selected one of the first and second output signals.

### Claim 5

A memory system comprising:
a first memory circuit;
a second memory circuit;
a first control line for receiving a split control signal, the split control signal having a first state and a second state;
means for accessing the first and second memory circuits in response to the split control signal, wherein the means for accessing accesses the first and second memory circuits independently when the split control signal is in the first state, and wherein the means for accessing accesses the first and second memory circuits jointly when the split control signal is in the second state.

### Claim 6 (depends on 5)

The memory system of claim 5, further comprising:
a first set of lines for receiving a first set of memory control signals, the first set of lines being coupled to the means for accessing; and
a second set of lines for receiving a second set of memory control signals, the second set of lines being coupled to the means for accessing, the means for accessing coupling the first set of lines to the first memory circuit and the second set of lines to the second memory circuit when the split control signal is in the first state.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the means for accessing couples a selected one of the first and second sets of lines to the first and second memory circuits when the split control signal is in the second state.

### Claim 8 (depends on 7)

The memory system of claim 7, further comprising a second control line for receiving a line set control signal, the line set control signal having a first state and a second state, wherein the means for accessing accesses the first and second memory circuits in response to the line set control signal, wherein the means for accessing couples the first set of lines to the first and second memory circuits when the split control signal is in the second state and the line set control signal is in the first state, and wherein the means for accessing couples the second set of lines to the first and second memory circuits when the split control signal is in the second state and the line set control signal is in the second state.

### Claim 9 (depends on 5)

The memory system of claim 5, further comprising:
a first output line coupled to the first memory circuit for receiving a first output signal; and
a second output line coupled to the second memory circuit for receiving a second output signal, the means for accessing routing the first and second output signals independently when the split control signal is in the first state.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the means for accessing routes only one of the first and second output signals at a time when the split control signal is in the second state.

### Claim 11 (depends on 9)

The memory system of claim 9, further comprising one or more additional memory circuits, wherein the means for accessing accesses the additional memory circuits in response to the split control signal.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the split control signal is a 1-bit signal.

### Claim 13 (depends on 11)

The memory system of claim 11, wherein the split control signal has a plurality of bits.

### Claim 14 (depends on 11)

The memory system of claim 11, wherein the memory circuits are arranged in a linear manner.

### Claim 15 (depends on 11)

The memory system of claim 11, wherein the memory circuits are arranged in a binary tree configuration.

### Claim 16 (depends on 1)

The memory system of claim 1, wherein the split control signal changes states during operation of the memory system.

### Claim 17

A method of operating a memory system comprising the steps of:
providing a plurality of memory circuits;
accessing the memory circuits independently in response to a first state of a first control signal;
accessing the memory circuits jointly in response to a second state of the first control signal.

### Claim 18 (depends on 17)

The method of claim 17, further comprising the step of selecting a set of input lines for accessing the memory circuits in response to a second control signal when the first control signal is in the second state.

### Claim 19 (depends on 17)

The method of claim 17, further comprising the step of selecting an output line of one of the memory circuits in response to the second control signal and selected signal on the selected set of input lines.