# US 5,708,570 A · Shrinkage-matched circuit package utilizing low temperature co-fired ceramic structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,570 A - Document ID: US5708570A - Status: Granted - Kind: A - Application number: 08/540,735 - Filed: 1995-10-11 - Granted: 1998-01-13 - Earliest claimed: 1995-10-11 - Assignees: Hughes Aircraft Company - Inventors: Paul W. Polinski, Sr. - Web page: https://patentgrep.com/patent/US5708570A ## CPC - H01G 2/12: Protection against corrosion (H01G2/10 takes precedence) - H05K 1/162: {incorporating printed capacitors} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass} - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 3/4611: {by laminating two or more circuit boards (H05K3/4652 takes precedence)} - H05K 3/4629: {laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets} - H05K 2201/0187: with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties - Y10T 428/24926: including ceramic, glass, porcelain or quartz layer - Y10T 428/24942: including components having same physical characteristic in differing degree - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A glass-ceramic substrate for encapsulating an electronic component, with at least two shrinkage control layers restricting shrinkage of the substrate during a co-firing process. The shrinkage control layers are chosen so that they have substantially the same shrinkage characteristics, during co-firing, as the buried electronic component. This results in substantially no differential shrinkage between the electronic component and the substrate, along predetermined directions, during co-firing. In addition, the thermal expansion coefficients of the substrate, shrinkage control layers and electronic component are chosen so that they substantially match, such that their thermal-induced contraction during the cooling phase of the co-firing process substantially match. In the preferred embodiment, the electronic component is buried within the layers of an LTCC structure. The shrinkage control layers are preferably implemented as Al.sub.2 O.sub.3 or TiO.sub.2 filled dielectric green tape layers on top and bottom LTCC layers. A buried capacitor LTCC package is specifically disclosed. ## Claims ### Claim 1 A shrinkage-matched circuit package having top and bottom sides, comprising: a plurality of stacked low temperature co-fired ceramic (LTCC) layer, said stack having top and bottom layers, at least one electronic component buried within said stacked layers, and first and second non-metallic-powder-filled dielectric green tape layers disposed on said top and bottom LTCC layers, respectively, so that shrinkage is restricted along directions parallel to length and width directions of said electronic component during a co-firing process, said powder-filled dielectric green tape layers and said at least one electronic component having substantially equal shrinkage characteristics during said co-firing process, said powder-filled dielectric green tape layers, said at least one electronic component and said plurality of LTCC layers having substantially equal thermal expansion coefficients so that their thermal-induced contraction substantially match during a cooling phase of said co-firing process. ### Claim 2 (depends on 1) The package of claim 1, wherein said non-metallic-powder-filled layers contain about 0.5 to 2 percent glass. ### Claim 3 (depends on 1) The package of claim 1, wherein said at least one electronic component comprises at least one capacitor. ### Claim 4 (depends on 3) The package of claim 3, wherein each of said at least one capacitor comprises: capacitor dielectric material buried within said stacked LTCC layers, and two electrically conductive layers buried within said stacked LTCC layers, and positioned on opposite sides of said capacitor dielectric material. ### Claim 5 (depends on 4) The package of claim 4, wherein said capacitor dielectric material and said powder-filled dielectric green tape layers comprise Al.sub.2 O.sub.3 or TiO.sub.2 dielectric green tape. ### Claim 6 (depends on 5) The package of claim 5, wherein said capacitor dielectric material is disposed within a cavity in one of said stacked LTCC layers. ### Claim 7 (depends on 6) The package of claim 6, wherein one of said electrically conductive layers is disposed on an LTCC layer located above said capacitor dielectric, and the other is disposed on an LTCC layer located below said capacitor dielectric. ### Claim 8 (depends on 1) The package of claim 1, further comprising a third non-metallic-powder-filled dielectric green tape layer on an LTCC layer located between said top and bottom LTCC layers, with at least three LTCC layers located above and below said third non-metallic-powder-filled layer, respectively. ### Claim 9 (depends on 8) The package of claim 8, wherein at least one electronic component is buried within the LTCC layers above and at least one other electronic component is buried within the LTCC layers below said third powder-filled layer. ### Claim 10 (depends on 9) The package of claim 9, wherein said electronic components comprise capacitors. ### Claim 11 (depends on 10) The package of claim 10, wherein each of said capacitors comprise: capacitor dielectric material buried within said stacked LTCC layers, and two electrically conductive layers buried within said stacked LTCC layers, and positioned on opposite sides of said capacitor dielectric material. ### Claim 12 (depends on 11) The package of claim 11, wherein said capacitor dielectric material is disposed within a cavity in one of said stacked LTCC layers. ### Claim 13 (depends on 12) The package of claim 12, wherein one of said electrically conductive layers is disposed on an LTCC layer located above said capacitor dielectric, and the other is disposed on an LTCC layer located below said capacitor dielectric.