# US 5,708,550 A · ESD protection for overvoltage friendly input/output circuits

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- Number: US 5,708,550 A
- Document ID: US5708550A
- Status: Granted
- Kind: A
- Application number: 08/736,113
- Filed: 1996-10-24
- Granted: 1998-01-13
- Earliest claimed: 1996-10-24
- Assignees: David Sarnoff Research Center, Inc.
- Inventors: Leslie Ronald Avery
- Web page: https://patentgrep.com/patent/US5708550A

## CPC

- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- H03K 19/00315: {in field-effect transistor circuits}
- H10D 89/611: {using diodes as protective elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An electrostatic discharge (ESD) protection circuit includes an input terminal, a power supply line and a source of reference potential. The circuit also includes a dummy supply line. A Schottky barrier diode is connected between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage. A first clamping structure is connected between the dummy supply line and the source of reference potential, and a second clamping structure is connected between the power supply line and the source of reference potential. A first clamping diode is connected between the input terminal and the dummy supply line and a second clamping diode is connected between the input terminal and the source of reference potential.

## Claims

### Claim 1

An ESD protection circuit comprising:
an input terminal;
power supply line for providing a power supply voltage;
a source of reference potential;
a Schottky barrier diode between the input terminal and the power supply line for blocking voltages from the input terminal which are greater than the power supply voltage;
a clamping circuit for clamping excess positive voltage at a higher voltage than the power voltage;
first clamping means between the input terminal and the clamping circuit; and
second clamping means for clamping negative voltages at the input terminal to the source of reference potential.

### Claim 2 (depends on 1)

An ESD protection circuit in accordance with claim 1 including a dummy supply line and a first portion of the clamping circuit is connected between the dummy supply line and the source of reference potential.

### Claim 3 (depends on 2)

An ESD protection circuit in accordance with claim 2 in which a second portion of the clamping circuit is connected between the power supply line and the source of reference potential.

### Claim 4 (depends on 3)

An ESD protection circuit in accordance with claim 3 in which the first clamping means is a semiconductor diode connected between the input terminal and the dummy line.

### Claim 5 (depends on 4)

An ESD protection circuit in accordance with claim 4 in which the second clamping means is a semiconductor diode connected between the input terminal and the source of reference potential.

### Claim 6 (depends on 5)

The ESD protection circuit in accordance with claim 5 in which each portion of the clamping circuit is a separate ESD protection structure.

### Claim 7 (depends on 6)

The ESD protection circuit in accordance with claim 6 in which the first portion of the clamping circuit is an ESD protection structure which will trigger within two to three volts above the maximum allowable supply voltage and will snap-back to a holding voltage which is only one to two volts above the maximum allowable supply voltage.

### Claim 8 (depends on 7)

The ESD protection circuit in accordance with claim 7 in which the second portion of the clamping circuit is an ESD protection structure which triggers at about one diode forward voltage drop below the maximum logic level and clamps at that voltage.