# US 5,708,536 A · RLL to NRZ decoder circuit in disk drive read/write channel

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- Number: US 5,708,536 A
- Document ID: US5708536A
- Status: Granted
- Kind: A
- Application number: 08/454,048
- Filed: 1995-05-30
- Granted: 1998-01-13
- Earliest claimed: 1995-05-30
- Assignees: Exar Corporation
- Inventors: Yihe Huang
- Web page: https://patentgrep.com/patent/US5708536A

## CPC

- G11B 20/1426: {conversion to or from block codes or representations thereof}
- G11B 20/1403: {characterised by the use of two levels}
- G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R)

## Abstract

The present invention is directed to a decoder circuit that can be operated at higher frequencies of a RLL clock. RLL data input from a disk drive is shifted through a first stage of the decoder circuit by the standard RLL clock. The RLL data is shifted from the first stage through a second stage of the decoder circuit by a modified RLL' clock that operates at a lower frequency than the RLL clock. In a preferred embodiment, RLL' clock operates at one-third the frequency of the RLL clock. The decoding step is accomplished within the period of one clock cycle of the slower RLL' clock, which affords the decoder circuit of the present invention a sufficient amount of time to decode the RLL data from the disk drive into NRZ data for the host. Since RLL' clock used in the decoding step is slower, the RLL clock used to generate RLL' clock and to clock data into the decoder circuit from the disk drive can be operated at a higher frequency than currently possible. This improvement in the speed of the RLL clock provides an improvement in the throughput of data from disk drive to host.

## Claims

### Claim 1

In a disk drive including a controller coupled to a read/write channel and a head/disk assembly, the read/write channel comprising:
a serial run-length limited (RLL) data input;
a first RLL clock input having a first frequency;
a first memory block coupled to said serial RLL data input and said first RLL clock input, said first memory block having a first parallel RLL data output, said first memory block further comprising:
a first flip-flop coupled to said serial RLL data input and said first RLL clock input, said first flip-flop having an output;
a second flip-flop coupled to said output of said first flip-flop and said first RLL clock input, said second flip-flop having an output; and
a third flip-flop coupled to said output of said second flip-flop and said first RLL clock input, said third flip-flop having an output;
a second RLL clock input having a second frequency Q different from said first frequency;
a second memory block coupled to said first parallel RLL data output and said second RLL clock input, said second memory block having a second parallel RLL data output, said second memory block further comprising:
a third memory block coupled to said first parallel RLL data output of said first memory block and said second RLL clock input, said third memory block having an output, said third memory block further comprising:
a first flip-flop coupled to said output of said first flip-flop of said first memory block and said second RLL clock input, said first flip-flop having an output;
a second flip-flop coupled to said output of said second flip-flop of said first memory block and said second RLL clock input, said second flip-flop having an output; and
a third flip-flop coupled to said output of said third flip-flop of said first memory block and said second RLL clock input, said third flip-flop having an output;
a fourth memory block coupled to said output of said third memory block and said second RLL clock input, said fourth memory block having an output, said fourth memory block comprising:
a first flip-flop coupled to said output of said first flip-flop of said third memory block and said second RLL clock input, said first flip-flop having an output;
a second flip-flop coupled to said output of said second flip-flop of said third memory block and said second RLL clock input, said second flip-flop having an output; and
a third flip-flop coupled to said output of said third flip-flop of said third memory block and said second RLL clock input, said third flip-flop having an output;
a fifth memory block coupled to said output of said fourth memory block and said second RLL clock input, said fifth memory block having an output, said fifth memory block comprising:
a first flip-flop coupled to said output of said first flip-flop of said fourth memory block and said second RLL clock input, said first flip-flop having an output;
a second flip-flop coupled to said output of said second flip-flop of said fourth memory block and said second RLL clock input, said second flip-flop having an output; and
a third flip-flop coupled to said output of said third flip-flop of said fourth memory block and said second RLL clock input, said third flip-flop having an output.

### Claim 2

In a disk drive including a controller coupled to a read/write channel and a head/disk assembly, the read/write channel comprising:
a serial run-length limited (RLL) data input;
a first RLL clock input having a first frequency;
a first memory block coupled to said serial RLL data input and said first RLL clock input, said first memory block having a first parallel RLL data output;
a second RLL clock input having a second frequency operating at one-third frequency of said first frequency; and
a second memory block coupled to said first parallel RLL data output and said second RLL clock input, said second memory block having a second parallel RLL data output.

### Claim 3 (depends on 2)

The read/write channel of claim 2 further comprising a decoding logic for converting said second parallel RLL data output into parallel nonreturn-to-zero (NRZ) data.

### Claim 4

A method of encoding a serial run-length limited (RLL) data input into a parallel nonreturn-to-zero (NRZ) data output comprising the steps of:
clocking the serial RLL data input into a first memory block with a first RLL clock signal;
separating the serial RLL data input into three parallel RLL data signals;
clocking said three parallel RLL data signals into a second memory block with a second RLL clock signal operating at one-third frequency of said first RLL clock signal;
coupling said three parallel RLL data signals to a decoding logic block; and
decoding said three parallel RLL data signals into two parallel NRZ data outputs.