# US 5,708,455 A · Active matrix display device

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- Number: US 5,708,455 A
- Document ID: US5708455A
- Status: Granted
- Kind: A
- Application number: 08/756,699
- Filed: 1996-11-26
- Granted: 1998-01-13
- Earliest claimed: 1994-04-22
- Assignees: Sony Corporation
- Inventors: Toshikazu Maekawa
- Web page: https://patentgrep.com/patent/US5708455A

## CPC

- G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters}
- G09G 3/3685: {Details of drivers for data electrodes}
- G11C 8/04: using a sequential addressing device, e.g. shift register, counter
- G11C 19/00: Digital stores in which the information is moved stepwise, e.g. shift registers
- H04N 3/127: {using liquid crystals}
- H04N 3/27: Circuits special to multi-standard receivers
- G09G 2310/0232: Special driving of display border areas
- G09G 2310/0283: Arrangement of drivers for different directions of scanning
- G09G 2340/0442: Handling or displaying different aspect ratios, or changing the aspect ratio
- G09G 2340/0464: Positioning
- G09G 2360/02: Graphics controller able to handle multiple formats, e.g. input or output formats
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

An active matrix display device comprises a plurality of pixels, a vertical scanning circuit, a horizontal addressing circuit, a wide input switch element and a normal input switch element. The plurality of pixels are arrayed in a matrix shape. The vertical scanning circuit sequentially selects pixels every line. The horizontal addressing circuit dot-sequentially addresses selected line pixels and has a shift register constituted by a number of multi-stage connected flip-flops, the number of which corresponds to the total number of rows of pixels. Each flip-flop is equipped with a pair of input/output terminals and a prescribed start pulse is transferred every stage. The wide input switch element inputs a start pulse to an input terminal of a flip-flop positioned at a leading stage during wide displaying. The normal input switch element inputs a start pulse to an input of a flip-flop positioned at a specific intermediate stage during normal displaying. It is therefore possible to switch over between a wide display and a normal display using a horizontal addressing circuit employing a single shift register.

## Claims

### Claim 1

An active matrix display device, comprising;
a plurality of pixels arrayed in a matrix shave;
a vertical scanning circuit for sequentially selecting pixels every line;
a horizontal addressing circuit for dot-sequentially addressing selected line pixels, the circuit having a shift register formed of a number of multi-stage connected flip-flops corresponding to a total number of rows of pixels, with each flip-flop being equipped with a pair of input/output terminals and a prescribed start pulse being transferred every stage;
a wide input switch element for inputting a start pulse to the input terminal of the flip-flop positioned at a leading stage during wide displaying;
a normal input switch element for inputting a start pulse to the input terminal of the flip-flop positioned at a specific intermediate stage during normal displaying; and
dummy input switch elements for load adjustment connected to input/output terminals of flip-flops in positions other than the leading stage and the specific intermediate stage.

### Claim 2 (depends on 1)

An active matrix display device according to claim 1 wherein a connection gate element is provided between input and output terminals of a pair of flip-flops positioned at a wide display and normal display joint in such a manner that a start pulse transfer occurring at the joint is in a defined direction during wide displaying, and start pulse transfer at the joint is stopped during normal displaying.

### Claim 3 (depends on 1)

An active matrix display device according to claim 1, wherein transfer gate elements are provided respectively between input/output terminals of pairs of flip-flops positioned at neighboring stages in such a manner that transfer of a start pulse is controlled so as to be in a forward direction or a reverse direction.

### Claim 4 (depends on 1)

An active matrix display device according to claim 1 including an input terminal of a flip-flop positioned at a head of temporarily redundant stages not concerned with pixel dot-sequential addressing for normal displaying, the input terminal having a potential fixing dement connected thereto.

### Claim 5 (depends on 4)

An active matrix display device according to claim 4 wherein said potential fixing element connects the input terminal to ground.

### Claim 6 (depends on 4)

An active matrix display device according to claim 4 wherein said potential fixing element connects the input terminal to a power supply.

### Claim 7 (depends on 3)

An active matrix display device according to claim 3 wherein said transfer gate elements are each comprised of a CMOS transistor.

### Claim 8 (depends on 3)

An active matrix display device according to claim 3 wherein said transfer gate elements are each comprised of an analog switch of a NMOS transistor.

### Claim 9 (depends on 3)

An active matrix display device according to claim 3 wherein each of said transfer gate elements are each comprised of an analog switch of a PMOS transistor.

### Claim 10 (depends on 1)

An active matrix display device according to claim 1 wherein said dummy input switch elements are each comprised of a transmission gate of a CMOS transistor.