# US 5,708,439 A · Method and apparatus for observing unknown codes on satellite positioning system

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- Number: US 5,708,439 A
- Document ID: US5708439A
- Status: Granted
- Kind: A
- Application number: 08/544,996
- Filed: 1995-10-30
- Granted: 1998-01-13
- Earliest claimed: 1995-10-30
- Assignees: Trimble Navigation Limited
- Inventors: Gary R. Lennen
- Web page: https://patentgrep.com/patent/US5708439A

## CPC

- G01S 19/32: Multimode operation in a single same satellite system, e.g. GPS L1/L2
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES

## Abstract

The method and apparatus for observing unknown codes on the Satellite Positioning System satellites are disclosed. The technique employs the parabolic high gain antenna to determine the energy spectrum of the unknown W code. The technique does not provide sufficient accuracy to implement the effective anti-spoofing device.

## Claims

### Claim 1

An apparatus for observing unknown codes on Satellite Positioning System, said apparatus comprising:
a RECEIVING MEANS for receiving a known C/A code modulated on L1 carrier frequency, for receiving an unknown Y code modulated on L1 carrier frequency signal, wherein a received L1 signal contains propagation noise; and wherein said Y code comprises a known P code and an unknown W code;
a MICROPROCESSOR SYSTEM connected to said RECEIVING MEANS for controlling said apparatus using a CONTROL signal;
a W SAMPLES STORAGE connected to said MICROPROCESSOR SYSTEM for permanently storing logged W code samples; and
at least one DIGITAL CHANNEL PROCESSING MEANS for:
(1) locally generating replica of said C/A code modulated on L1 carrier frequency signal;
(2) locally generating replica of said P code modulated on L1 carrier frequency signal, wherein said locally generated replica of L1 signal does not contain propagation noise;
(3) extracting an estimate of said Y code from said L1 signal, wherein said estimate signal contains propagation noise;
(4) correlating a locally generated replica of C/A code with a received L1 code for obtaining code and carrier lock to the L1 C/A code signal;
(5) removing said P code from said locally extracted estimate of said L1Y code to obtain a locally extracted estimate of said L1 W code;
(6) logging said L1 W-code estimates in a DATA MEMORY, at a time mark controlled by said MICROPROCESSOR; and
(7) transferring data logged in said DATA MEMORY to a W SAMPLES STORAGE for further analysis.

### Claim 2 (depends on 1)

The system of claim 1, wherein said RECEIVING MEANS further comprises:
a PARABOLIC DISH ANTENNA MEANS for receiving said L1 satellite signal;
a FILTER/LNA MEANS conductively connected to said PARABOLIC ANTENNA MEANS for performing filtering and low noise amplification of said L1 signal, wherein said FILTER/LNA determines the signal/noise ratio of the received L1 signal L1;
a DOWNCONVERTER MEANS conductively connected to said FILTER LNA MEANS for mixing and converting said L1 signal; and
an IF PROCESSOR MEANS conductively connected to said DOWNCONVERTER MEANS for transforming said converted L1 signal into digitally sampled quadrature versions (IL1, QL1) of L1 signal.

### Claim 3 (depends on 2)

The system of claim 2 further comprising a FREQUENCY SYNTHESIZER; an ADJUSTABLE FREQUENCY SYNTHESIZER MEANS conductively connected to said FREQUENCY SYNTHESIZER, conductively connected to said IF PROCESSOR MEANS, conductively connected to said DOWNCONVERTER MEANS, and conductively connected to at least one said DIGITAL CHANNEL PROCESSING MEANS, wherein said ADJUSTABLE FREQUENCY SYNTHESIZER MEANS generates several timing signals.

### Claim 4 (depends on 2)

The system of claim 2, wherein said FILTER/LNA MEANS further comprises:
a BANDPASS FILTER MEANS connected to said PARABOLIC ANTENNA for filtering said L1 signal; and a LOW NOISE AMPLIFIER (LNA) connected to said BANDPASS FILTER MEANS for amplifying said filtered L1 signal.

### Claim 5 (depends on 3)

The system of claim 3, wherein said ADJUSTABLE FREQUENCY SYNTHESIZER further includes:
a FREQUENCY SYNTHESIZER block being controlled by a CONTROL signal generated by a MICROPROCESSOR SYSTEM; and
a DIVIDE BY 2 block coupled to said FREQUENCY SYNTHESIZER block for dividing by 2 the frequency of the signal generated by said FREQUENCY SYNTHESIZER block; wherein said ADJUSTABLE FREQUENCY SYNTHESIZER generates a 5 MHz signal.

### Claim 6 (depends on 3)

The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:
a PHASE DETECTOR MEANS for comparing phases of two signals, first said signal being an output signal from said MASTER OSCILLATOR MEANS, second said signal being generated by said FREQUENCY SYNTHESIZER MEANS local reference signal, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of said two signals;
a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise, wherein an output LOOP FILTER MEANS voltage signal includes a low frequency voltage noise;
a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein a voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output signal is locked to said reference signal; and wherein said VCO nominal output signal is used as 1st local oscillator (LO1) signal;
a first DIVIDER MEANS connected to said VCO to divide said VCO output signal to obtain 2nd local oscillator (LO2) signal; and
a second DIVIDER MEANS connected to said first DIVIDER MEANS to divide said 2nd LO2 signal to obtain sampling clock (SCLK).

### Claim 7 (depends on 3)

The system of claim 3, wherein said FREQUENCY SYNTHESIZER MEANS further comprises:
a "Divide by 5" block;
a PHASE DETECTOR MEANS connected to said block "Divide by 5" for comparing 5 MHz input signal from said MASTER OSCILLATOR MEANS with 5 MHZ signal from said "Divide by 5" block, wherein minimum voltage output signal from said PHASE DETECTOR MEANS represents maximum phase alignment of two said 5 MHZ signals;
a LOOP FILTER MEANS connected to said PHASE DETECTOR MEANS for filtering out high frequency voltage noise;
a VOLTAGE CONTROLLED OSCILLATOR (VCO) MEANS connected to said LOOP FILTER MEANS, wherein voltage signal at the input of said VCO causes frequency change in said VCO output signal, and wherein said VCO nominal output 1400 MHz signal is locked to said 5 MHZ reference signal; and wherein said 1400 MHz VCO output signal is used as a 1st local oscillator (LO1);
a "Divide by 8" block connected to said VCO to divide said 1400 MHZ VCO output signal by 8 to obtain a 175 MHZ signal used as a 2nd LO2; and
a "Divide by 7" block connected to said "Divide by 8" block to divide said 175 MHZ signal by 7 to obtain a 25 MHZ signal used as a sampling clock (SCLK).

### Claim 8 (depends on 2)

The system of claim 2, wherein said DOWNCONVERTER MEANS further comprises:
a MULTIPLIER MEANS for multiplying said L1 signal with said 1st LO1 signal, wherein a mixed signal is produced;
a BANDPASS FILTER MEANS connected to said MULTIPLIER MEANS for filtering said mixed signal; and ..
an AMPLIFIER MEANS connected to said BANDPASS FILTER MEANS for amplifying said filtered signal; wherein said L1 signal is downconverted from the 1575.42 MHz frequency to a frequency of 175.42 MHz.

### Claim 9 (depends on 2)

The system of claim 2, wherein said IF PROCESSOR MEANS further comprises:
a POWER SPLITTER MEANS connected to said DOWNCONVERTER MEANS and to said FREQUENCY SYNTHESIZER MEANS for power splitting said L1 signal into two signals;
a first MULTIPLIER MEANS for multiplying said L1 signal with an inphase (I) version of said 2nd LO2 signal to produce an IL1 signal;
a second MULTIPLIER MEANS for multiplying said L1 signal with a quadrature (Q) version of said 2nd LO2 signal to produce a QL1 signal;
a first LOWPASS FILTER MEANS connected to said first MULTIPLIER MEANS for filtering said first mixed signal;
a second LOWPASS FILTER MEANS connected to said second MULTIPLIER MEANS for filtering said second mixed signal;
a first AMPLIFIER MEANS connected to said first LOWPASS FILTER MEANS for amplifying said IL1 signal;
a second AMPLIFIER MEANS connected to said second LOWPASS FILTER MEANS for amplifying said QL1 signal;
a first one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said first AMPLIFIER MEANS for performing 1-bit quantization operation on said IL1 signal;
a second one-bit analog-to-digital (A/D) CONVERTER MEANS connected to said second AMPLIFIER MEANS for performing 1-bit quantization operation on said QL1 signal;
a first FLIP-FLOP MEANS (FF1) connected to said first one-bit A/D CONVERTER for sampling said IL1 signal, wherein said sampling operation is performed by clocking said IL1 signal through said FF1 at sampling clock (SCLK) rate; and
a second FLIP-FLOP MEANS (FF2) connected to said second one-bit A/D CONVERTER for sampling said QL1 signal, wherein said sampling operation is performed by clocking said QL1 signal through said FF2 at sampling clock (SCLK) rate.

### Claim 10 (depends on 1)

The system of claim 1, wherein each said DIGITAL CHANNEL PROCESSING MEANS further comprises:
an L1 C/A TRACKER MEANS for tracking L1 C/A code;
a SAMPLED W CODE EXTRACTOR connected to said L1 C/A TRACKER MEANS for extracting and storing samples of the unknown W code from a single satellite; and
a MICROPROCESSOR MEANS system connected to said L1 TRACKER MEANS and to said SAMPLED W CODE EXTRACTOR;
wherein said L1 C/A TRACKER MEANS is fed by digitized inphase IL1 and quadrature QL1 of L1 signal outputted by said IF PROCESSOR MEANS; and
wherein said SAMPLED W CODE EXTRACTOR is fed by Ys, P, and X1A signals outputted by said L1 C/A TRACKER MEANS; and
wherein said SAMPLED W CODE EXTRACTOR processes the signals Ys, P, and X1A to form samples of the unknown W code which are subsequently logged by said MICROPROCESSOR SYSTEM; and
wherein said L1 C/A TRACKER MEANS and said SAMPLED W CODE EXTRACTOR are synchronously clocked by said SCLK signal outputted by said FREQUENCY SYNTHESIZER MEANS; and
wherein said MICROPROCESSOR MEANS system is fed by output signals from said L1 C/A TRACKER MEANS and from said SAMPLED W CODE EXTRACTOR; and
wherein said L1 C/A TRACKER MEANS and said SAMPLED W CODE EXTRACTOR are fed by a CONTROL signal from said MICROPROCESSOR MEANS.

### Claim 11 (depends on 10)

The system of claim 10, wherein said L1 C/A TRACKER MEANS further comprises:
a carrier numerically controlled oscillator (CARRIER NCO MEANS);
a CARRIER MIXER MEANS connected to said CARRIER NCO MEANS for multiplying outputted by said IF PROCESSOR MEANS digitized inphase IL1 and QL1 signals having carrier frequency with outputted by said CARRIER NCO. MEANS inphase and quadrature components of digital carrier; wherein said CARRIER MIXER MEANS outputs inphase IL1 and quadrature QL1 signals having zero carrier frequency;
a CODE MIXER 1 MEANS connected to said CARRIER MIXER MEANS for code correlating said CARRIER MIXER MEANS output signals with a locally generated replica of C/A code; wherein when said L1 TRACKER MEANS's carrier tracking loop is closed via said CARRIER NCO MEANS the CARRIER MIXER's input to said CODE MIXER 1 MEANS represents the satellite signal L1 C/A code; and wherein said CODE MIXER 1 MEANS performs said code correlation at 3 time points (early, punctual and late) on the autocorrelation function graph creating an early, a punctual and a late sample of the autocorrelation function;
a block CORRELATORS MEANS connected to said CODE MIXER 1 MEANS for integrating said early, punctual and late samples of said autocorrelation function over an integer number of EPOCH signals; wherein said CORRELATORS MEANS output signal is fed to said MICROPROCESSOR MEANS system at a rate of L1 C/A code EPOCH, and wherein said MICROPROCESSOR MEANS uses said CORRELATORS MEANS output signal to develop feedback signals for the L1 carrier tracking loop and for the L1 code tracking loop;
a CODE GENERATOR MEANS connected to said CORRELATORS block for providing a locally generated replica of C/A code, a locally generated replica of P code, an EPOCH signal, and an X1A signal; and
a code numerically controlled oscillator (CODE NCO MEANS) connected to said block CORRELATORS MEANS and connected to said CODE GENERATOR MEANS for driving said CODE GENERATOR MEANS;
wherein when said L1 C/A TRACKER is carrier locked to the tracked satellite the satellite's C/A code power is observed in the I output of said CARRIER MIXER and the satellite's P(Y) code power is observed in the Q output of said CARRIER MIXER; and
wherein by tracking L1 C/A code a baseband version of the satellite's P(Y) code is generated; and
wherein the L1 C/A TRACKER's output signal Ys represents a baseband estimate of the Y code of the tracked satellite; and
wherein the X1A output of said CODE GENERATOR is a standard P code generator timing signal that refers to a particular state of the X1A register.

### Claim 12 (depends on 10)

The system of claim 10, said SAMPLED W CODE EXTRACTOR further comprising:
a CODE MIXER 2 MEANS for mixing P code with Ys code, wherein P code and Ys code are generated by said L1 C/A TRACKER; and wherein said CODE MIXER 2 generates Ws code representing the incoming satellite Y code with P code removed;
an n-BIT SHIFT REGISTER coupled to said CODE MIXER 2 for maintaining the last n sampled bits of the Ws signal;
a DATA MEMORY block coupled with said n-BIT SHIFT REGISTER, wherein every n-th clock signal SCLK the output of said n-BIT SHIFT REGISTER is read into said DATA MEMORY;
an ADDRESSING COUNTER coupled to said DATA MEMORY block and addressing said DATA MEMORY block, wherein said ADDRESSING COUNTER increments the memory address value every n-th clock signal SCLK;
a 2-INPUT AND GATE gating the CONTROL and X1A signals for initiating the sample data collection process by said DATA MEMORY block at a known time in the GPS week and for synchronizing the logging process and for allowing repeated controlled observation of the encrypted signals, said 2-INPUT AND GATE generating a RESET signal;
a DIVIDE BY n block connected to said L1 C/A TRACKER for generating a second clock signal by dividing the clock SCLK signal by n, wherein said DIVIDE BY n block is reset by said RESET signal, and wherein said second clock signal clocks said ADDRESSING COUNTER; and
wherein when said DATA MEMORY is filled said DATA MEMORY is read by said MICROPROCESSOR SYSTEM and transferred to said permanent storage W SAMPLES STORAGE.

### Claim 13

A method for observing unknown codes on SPS; said method employing a system comprising a RECEIVING MEANS, at least one DIGITAL CHANNEL PROCESSING MEANS, and a W SAMPLES STORAGE; said method comprising the steps of:
providing said RECEIVING MEANS, said W SAMPLES STORAGE, and at least one said DIGITAL CHANNEL PROCESSING MEANS;
receiving a known L1 C/A code modulated on L1 carrier frequency, and an unknown Y code modulated on L1 carrier frequency signal by said RECEIVING MEANS; wherein a received L1 signal contains propagation noise; and wherein said Y code comprises a known P code and an unknown W code;
generating a local replica of said C/A code and a local replica of said P code modulated on L1 carrier frequency signal by each said DIGITAL CHANNEL PROCESSING MEANS;
extracting an estimate of said Y code from said L1 signal by each said DIGITAL CHANNEL PROCESSING MEANS;
correlating a locally generated replica of C/A code with the received L1 code for obtaining code and carrier lock to the L1 C/A code signal;
removing said P code from said locally extracted estimate of said L1Y code by each said DIGITAL CHANNEL PROCESSOR to obtain a locally extracted estimate of said L1 W code;
logging said L1 W code estimate in a DATA MEMORY at a time mark controlled by a MICROPROCESSOR; and
transferring a logged sampled W code from said DATA MEMORY to said W SAMPLES STORAGE for further processing.

### Claim 14 (depends on 13)

The method of claim 13, said RECEIVING MEANS further comprising a FILTER/LNA MEANS, a DOWNCONVERTER MEANS, an IF PROCESSOR MEANS, and a FREQUENCY SYNTHESIZER MEANS; wherein said step of receiving L1 satellite signal further comprises the steps of:
receiving said L1 satellite signal by said PARABOLIC ANTENNA MEANS;
performing filtering and low noise amplification of said L1 signal by said FILTER/LNA MEANS, wherein said FILTER/LNA MEANS determines the signal/noise ratio of the received signal L1;
converting said L1 signal by said DOWNCONVERTER MEANS;
transforming said converted L1 signal into digitally sampled quadrature versions of L1 signal (IL1, QL1) by said IF PROCESSOR MEANS; and
generating several timing signals by said FREQUENCY SYNTHESIZER MEANS.

### Claim 15 (depends on 13)

The method of claim 13, each said DIGITAL CHANNEL PROCESSING MEANS further comprising a MICROPROCESSOR MEANS system; said method further comprising the steps of:
tracking L1 C/A code by said L1 C/A TRACKER MEANS;
feeding said SAMPLED W CODE EXTRACTOR MEANS by Ys, P code, and X1A signals generated by said L1 C/A TRACKER MEANS;
extracting and storing samples of the unknown W code from said Ys, P, and X1A signals by said SAMPLED W CODE EXTRACTOR MEANS; and
feeding said W SAMPLES STORAGE by the samples of the unknown W code under control of said MICROPROCESSOR MEANS system.

### Claim 16 (depends on 15)

The method of claim 15, said L1 C/A TRACKER MEANS further comprising a (CARRIER NCO MEANS), a CARRIER MIXER MEANS, a CODE MIXER 1 MEANS, a block CORRELATORS MEANS, a CODE GENERATOR MEANS, and a code numerically controlled oscillator (CODE NCO MEANS); said method further comprising the steps of:
multiplying by said CARRIER MIXER MEANS outputted by said IF PROCESSOR MEANS digitized inphase IL1 and QL1 signals having carrier frequency with outputted by said CARRIER NCO MEANS 1 inphase and quadrature components of digital carrier; wherein said CARRIER MIXER MEANS outputs inphase IL1 and quadrature QL1 signals having zero carrier frequency;
providing a locally generated replica of C/A code, a locally generated replica of P code, an EPOCH signal, and an X1A signal by said CODE GENERATOR MEANS;
driving said CODE GENERATOR MEANS by said CODE NCO MEANS;
correlating by said CODE MIXER 1 MEANS the inphase IL1 and the quadrature QL1 signals having zero carrier frequency with said locally generated replica of C/A code; and
integrating by the block CORRELATORS MEANS the early, punctual and late samples of the autocorrelation function generated by said CODE MIXER 2 MEANS over an integer number of said EPOCH signals;
wherein when said L1 C/A TRACKER is carrier locked to the tracked satellite the satellite's C/A code power is observed in the I output of said CARRIER MIXER and the satellite's P(Y) code power is observed in the Q output of said CARRIER MIXER; and
wherein by tracking L1 C/A code a baseband version of the satellite's P(Y) code is generated; and
wherein the L1 C/A TRACKER's output signal Ys represents a baseband estimate of the Y code of the tracked satellite; and
wherein the X1A output of said CODE GENERATOR is a standard P code generator timing signal that refers to a particular state of the X1A register.

### Claim 17 (depends on 15)

The method of claim 15, said SAMPLED W CODE EXTRACTOR further comprising a CODE MIXER 2 MEANS, an n-BIT SHIFT REGISTER, a DATA MEMORY block, an ADDRESSING COUNTER, a 2-INPUT AND GATE, and a DIVIDE BY n block; said method comprising the steps of:
mixing by said CODE MIXER 2 MEANS P code with Ys code;
generating a Ws code representing the incoming satellite Y code with P code removed by said CODE MIXER 2;
maintaining the last n sampled bits of the Ws signal by said n-BIT SHIFT REGISTER;
reading into said DATA MEMORY block every n-th clock signal SCLK the output of said n-BIT SHIFT REGISTER; addressing by said ADDRESSING COUNTER said DATA MEMORY block, wherein said ADDRESSING COUNTER increments the memory address value every n-th clock signal SCLK;
initiating the sample data collection process by said DATA MEMORY block at a known time in the GPS week, synchronizing the logging process, and allowing repeated controlled observation of the encrypted signals by said 2-INPUT AND GATE, wherein said 2-INPUT AND GATE block gates the CONTROL and X1A signals and generates a RESET signal;
generating a second clock signal by dividing the clock SCLK signal by n by said DIVIDE BY n block; wherein said DIVIDE BY n block is reset by said RESET signal, and wherein said second clock signal clocks said ADDRESSING COUNTER; and
wherein when said DATA MEMORY is full of samples said DATA MEMORY is read by said MICROPROCESSOR SYSTEM and transferred to said permanent storage W SAMPLES STORAGE.

### Claim 18

A method for logging the sampled W code generated by the Satellite Positioning System (SPS) comprising the steps of:
selecting a satellite-vehicle (SV) to be observed;
observing the selected SV by steering a PARABOLIC DISH ANTENNA to azimuth and elevation of said SV;
searching by a L1 C/A TRACKER an L1 C/A code signal generated by said SV;
locking to said L1 C/A code by closing the code and carrier tracking loops by said L1 C/A TRACKER;
synchronizing P and X1A signals generated by a CODE GENERATOR with said SV satellite L1 C/A signal;
aligning an ADJUSTABLE FREQUENCY OSCILLATOR to said SV;
extracting unknown W code signals from said L1 C/A signals by a W CODE EXTRACTOR;
logging sampled W code signals by a DATA MEMORY block;
transferring the logged sampled W code from said DATA MEMORY to a W SAMPLE STORAGE by a MICROPROCESSOR system; and
stopping the logging process when said W SAMPLE STORAGE is filled.