# US 5,708,391 A · High frequency differential filter with CMOS control

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- Number: US 5,708,391 A
- Document ID: US5708391A
- Status: Granted
- Kind: A
- Application number: 08/643,140
- Filed: 1996-05-02
- Granted: 1998-01-13
- Earliest claimed: 1996-05-02
- Inventors: Michael Altmann; Bernard Guay
- Web page: https://patentgrep.com/patent/US5708391A

## CPC

- H03H 11/1291: {Current or voltage controlled filters}
- H03H 11/1213: {using transistor amplifiers (H03H11/1204 takes precedence; parallel-T filters H03H11/1295)}
- H03F 2203/45504: the CSC comprising more than one switch
- H03F 2203/7203: the gated amplifier being switched on or off by a switch in the bias circuit of the amplifier controlling a bias current in the amplifier
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03F: AMPLIFIERS

## Abstract

A programmable high frequency active filter comprises a plurality of basic building blocks connected in parallel. A basic building block includes a transistor pair connected in a differential amplifier configuration, an impedance connected between the emitters of the transistors and a switching block for applying the necessary bias current to the transistors. The transfer function of the filter is programmed with a digital word, the length of which determines the number of basic building blocks included in the configuration. In this way, the equivalent high frequency impedance of the filter is controlled by selecting the configuration and the value of the impedance of each building block.

## Claims

### Claim 1

A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a differential amplifier comprising a first and a second transistor;
an impedance connected between the emitters of said first and second transistors, for introducing a high frequency zero in said differential output signal; and
a switching block for selectively including said high frequency zero in said output differential signal according to a digital control signal.

### Claim 2 (depends on 1)

A filter as claimed in claim 1, wherein said first transistor is biased with a first current source, and said second transistor is biased with a second current source.

### Claim 3

A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a plurality (N) of differential amplifiers connected in parallel, a differential amplifier A.sub.i comprising a first and a second transistor;
a like plurality (N) of impedance units, an impedance unit Z.sub.i being connected between the emitters of said first and second transistors of said differential amplifier A.sub.i for introducing a high frequency zero in said output differential signal;
a like plurality (N) of switching blocks, a switching block SW.sub.i for selectively including said high frequency zero in said output differential signal according to a digital control signal.

### Claim 4 (depends on 3)

A filter as claimed in claim 3, wherein said first transistor is biased with a first current source, and said second transistor is biased with a second current source.

### Claim 5 (depends on 1)

A filter as claimed in claim 1, wherein said impedance is a reactance.

### Claim 6 (depends on 1)

A filter as claimed in claim 1, wherein said impedance is a capacitive network.

### Claim 7 (depends on 1)

A filter as claimed in claim 1, wherein said first and said second transistors are matched to each other.

### Claim 8 (depends on 2)

A filter as claimed in claim 2, wherein said switching block comprises:
a first switch for switching the bias current produced by said first current source between the emitter and the collector of said first transistor; and
a second switch for switching the bias current produced by said second current source between the emitter and the collector of said second transistor.

### Claim 9 (depends on 8)

A filter as claimed in claim 8, wherein said first switch comprises a CMOS pair of a first and a third MOS device and said second switch comprises a CMOS pair of a second and a fourth MOS device.

### Claim 10 (depends on 9)

A filter as claimed in claim 9, wherein said first and said second MOS devices are PMOS transistors, and said third and fourth MOS devices are NMOS transistors.

### Claim 11 (depends on 9)

A filter as claimed in claim 9, wherein said first MOS device is connected with the drain and source between the emitter of said first transistor and said first current source, and said third MOS device is connected with the source and drain between the collector of said first transistor and said first current source.

### Claim 12 (depends on 9)

A filter as claimed in claim 9, wherein said second MOS device is connected with the drain and source between the emitter of said second transistor and said second current source, and said fourth MOS device is connected with the source and drain between the collector of said second transistor and said second current source.

### Claim 13 (depends on 9)

A filter as claimed in claim 9, wherein the gates of all said MOS devices are connected to receive said digital control signal.

### Claim 14 (depends on 3)

A filter as claimed in claim 3, wherein said impedance unit Z.sub.i is a capacitance.

### Claim 15 (depends on 4)

A filter as claimed in claim 4, wherein said switching block SW.sub.i comprises:
a first switch for commuting the bias current produced by said first current source between the emitter and the collector of said first transistor; and
a second switch for commuting the bias current produced by said second current source between the emitter and the collector of said second transistor.

### Claim 16 (depends on 15)

A filter as claimed in claim 15, wherein said first switch comprises a first CMOS pair of a first and a third MOS device, and said second switch comprises a second pair of a second and a fourth MOS device.

### Claim 17 (depends on 16)

A filter as claimed in claim 16, wherein said first and said second MOS devices are PMOS transistors, and said third and fourth MOS devices are NMOS transistors.

### Claim 18

A programmable high frequency active filter for receiving a differential input signal and providing a differential output signal, said filter comprising:
a differential amplifier comprising a first and second transistor, said first transistor having a first load resistor and being biased with a first bias current source, said second transistor having a second load resistor and being biased with a second bias current source;
a capacitive network connected between the emitters of said first and second transistors for providing a frequency dependent differential voltage gain for said amplifier;
a first MOS device connected with the drain and source between the emitter of said first transistor and said first current source;
a second MOS device connected with the drain and source between the emitter of said second transistor and said second current source;
a third MOS device connected with the source and drain between the collector of said first transistor and said first current source; and
a fourth MOS device connected with the source and drain between the collector of said second transistor and said second current source;
wherein the gates of all said MOS devices are connected to receive a digital control signal.

### Claim 19 (depends on 1)

A filter as claimed in claim 1, wherein said differential input signal has a format compatible with transmission over a differential medium.

### Claim 20 (depends on 19)

A filter as claimed in claim 19, wherein said differential medium is any of a twisted telephone pair, a pair of complimentary striplines, and a ribbon cable.

### Claim 21 (depends on 1)

A filter as claimed in claim 1, wherein said differential input signal is a digital signal.

### Claim 22 (depends on 1)

A filter as claimed in claim 1, wherein said differential input signal is an analog signal.
