# US 5,708,388 A · Single current source current generating circit for periodically activating and deactivating portions of an IC > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,388 A - Document ID: US5708388A - Status: Granted - Kind: A - Application number: 08/669,016 - Filed: 1996-06-24 - Granted: 1998-01-13 - Earliest claimed: 1994-12-15 - Assignees: International Business Machines Corporation - Inventors: Paul Scot Carlile - Web page: https://patentgrep.com/patent/US5708388A ## CPC - G05F 3/242: {with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A semiconductor chip incorporating a current generating circuit that will both power-down selected circuitry during inactive or standby periods and yet maintain a bias current to other parts of the chip. More specifically, the current generating circuit has output lines for providing output currents that mirror the current source during chip power-on operation periods. During chip power-down operation periods, the current generating circuit uses a current bias generator to supply current only to circuits needing to be operational during a partial chip operational mode. ## Claims ### Claim 1 A current generator comprising: input means for receiving a control current; first output means comprising a current mirror of the input means for providing a first output current over a first output line when the control current is at a sufficient magnitude for activating the input means; and bias means, coupled to the input means and to the first output means for providing a second output current over the first output line when the control current is at an insufficient magnitude to activate the input means; and second output means comprising a current mirror of the input means for providing a third output current over a second output line when the control current is at the sufficient magnitude. ### Claim 2 (depends on 1) The current generator of claim 1, wherein the input means includes an input transistor having its source coupled to a ground and its gate coupled to the first output means, the second output means, and the bias means. ### Claim 3 (depends on 2) The current generator of claim 2, wherein the first output means includes an output transistor having its gate coupled to the input transistor, its source coupled to the ground, and its drain coupled to the first output line. ### Claim 4 (depends on 2) The current generator of claim 2, wherein the second output means includes an output transistor having its gate coupled to the input transistor, its source coupled to the ground, and its drain coupled to the second output line. ### Claim 5 (depends on 2) The current generator of claim 2, wherein the bias means includes: a first bias transistor having its gate coupled to the input transistor, its source coupled to the ground, and its drain coupled to a first node; a resistive element coupled between a power supply and the first node; and a second bias transistor, having its gate coupled to the first node, its source coupled to the ground, and its drain coupled to the first output line, for supplying the second output current to the first output line when the control current is at the insufficient magnitude. ### Claim 6 An integrated circuit, comprising: a) a first circuit for processing received signals for the integrated circuit; b) a second circuit for processing received signals for the integrated circuit; c) first current generating means, coupled to a current source, and to the first and second circuit through a first and second output line, respectively, for providing current to the first and second circuit when the first current generating means receives current from the current source having sufficient magnitude for activating the first current generating means; and e) second current generating means coupled directly to the current source for providing current only to the first circuit when the second current generating means receives a signal from the current source for activating the second current generating means. ### Claim 7 (depends on 8) The integrated circuit of claim 8, wherein the first current generating means includes an input transistor with its source coupled to ground, and its gate coupled to the second current generating means. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the first output line includes a first transistor having its gate coupled to the input transistor and its source coupled to the ground. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the second output line includes a second transistor having its gate coupled to the input transistor and its source coupled to the ground. ### Claim 10 (depends on 7) The integrated circuit of claim 7, wherein the second current generating means includes: a first bias transistor having its gate coupled to the input transistor, its source coupled to the ground, and its drain coupled to a first node; a resistive element coupled between a power supply and the first node; end a second bias transistor, having its gate coupled to the first node, its source coupled to the ground, and its drain coupled to the first output line, for supplying the current only to the first circuit when the second current generating means receives the signal from the current source. ### Claim 11 An integrated circuit having a current generating circuit that comprises: a) input means for receiving a reference current, wherein the input means includes an input transistor with a source coupled to a ground; b) first and second output means, coupled to the input means as current mirrors, for generating first and second output currents, wherein the first output means includes a first transistor having a gate coupled to the input transistor and a source coupled to the ground and a drain coupled to a first output line, and the second output means includes a second transistor having a gate coupled to the input transistor and a source coupled to the ground and a drain coupled to a second output line; and c) bias means, coupled to the input means and the second output line, for generating a third output current when the input means is not receiving the reference current, wherein the bias means includes: a first bias transistor having a gate coupled to the input transistor and a source coupled to the ground and a drain coupled to a first node; a resistive element coupled between a power supply and the first node; and a second bias transistor, having a gate coupled to the first node, a source coupled to the ground and a drain coupled to the second output line, for supplying the third output current.