# US 5,708,385 A · Weighted addition circuit

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- Number: US 5,708,385 A
- Document ID: US5708385A
- Status: Granted
- Kind: A
- Application number: 08/657,757
- Filed: 1996-05-31
- Granted: 1998-01-13
- Earliest claimed: 1995-06-02
- Assignees: Yozan Inc.; Sharp Kabushiki Kaisha
- Inventors: Guoliang Shou; Sunao Taktori; Makoto Yamamoto
- Web page: https://patentgrep.com/patent/US5708385A

## CPC

- G06G 7/14: for addition or subtraction (of vector quantities G06G7/22 {; computing the average by addition; differential amplifiers H03F3/45})
- G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00)

## Abstract

A weighted addition circuit contains a plurality of resistances, each of which is connected to a common output at one terminal and to different input voltages at the other terminal. The voltage at the common output terminal is a balance voltage of the input resistances. The common output terminal is connected to an amplifier having an odd number of stages of inverters and a feedback resistance connecting the output of the last inverter stage to the input of the first inverter stage. Grounded low pass capacitors and/or balance resistors are also be included in the amplifier to improve the stability of the circuit and prevent undesirable oscillation. Providing a circuit containing a balance voltage of the parallel-connected input resistances allows for precise weighted addition of any number of inputs while still maintaining a small and simple circuit structure.

## Claims

### Claim 1

A weighted addition circuit comprising:
a plurality of input resistances each having an input terminal and an output terminal, each of said input terminals receiving an input voltage and each of said output terminals being connected to a common output, wherein a sum of said input voltages is a minuend;
a first amplifying circuit connected to said common output of said input resistances, said first amplifying circuit comprising three stages of serially connected inverters and a feedback resistance for feeding back an output of an inverter from a last stage to an input of an inverter from a first stage;
a first intermediate resistance having input and output terminals, said input terminal of said first intermediate resistance connected to an output of said first amplifying circuit;
a second intermediate resistance having input and output terminals, said input terminal of said second intermediate resistance receiving an input voltage as a subtrahend;
a second amplifying circuit connected to said output terminals of said first and second intermediate resistances, said second amplifying circuit containing three stages of serially connected inverters and a feedback resistance for feeding back an output of an inverter from a last stage to an input of an inverter from a first stage; and
a capacitance connected between the output of a last stage of said inverters in at least one of said first and second amplifying circuits and ground to increase circuit stability.

### Claim 2 (depends on 1)

A weighted addition circuit as claimed in claim 1, wherein a first ratio between a first composite resistance derived from said plurality of said input resistances and said feedback resistance in said first amplifying circuit is smaller by at least 1 than a second ratio between said second intermediate resistance and said feedback resistance in said second amplifying circuit.

### Claim 3 (depends on 1)

A weighted addition circuit as claimed in claim 1, further comprising at least one balance resistance having one terminal connected between two inverters in said first or second amplifying circuit and the other terminal connected to a power supply or to the ground.