# US 5,708,380 A · Test for hold time margins in digital systems

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- Number: US 5,708,380 A
- Document ID: US5708380A
- Status: Granted
- Kind: A
- Application number: 08/594,737
- Filed: 1996-01-31
- Granted: 1998-01-13
- Earliest claimed: 1996-01-31
- Assignees: Hughes Electronics Corporation
- Inventors: William D. Farwell
- Web page: https://patentgrep.com/patent/US5708380A

## CPC

- H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A flip-flop circuit that includes a first NAND gate (11) responsive to a D input to the flip-flop circuit and a first mode control signal for providing a first NAND gate output; a second NAND gate (12) responsive to a serial scan input to the flip-flop circuit and a second mode control signal for providing a second NAND gate output; an inverter (21) responsive to the first NAND gate output for providing an inverter output; a first transmission gate responsive to the first NAND gate output and the second NAND gate output for providing a first transmission gate output, the first transmission gate output being a replica of the inverter output when the first mode control signal is of a first logical state and the second mode control signal is of a second logical state, and the first transmission gate output being of high impedance when the first mode control signal is of the second logical state and the second mode control signal is of the first logical state; a second transmission gate (32) responsive to the first NAND gate output and the second NAND gate output for providing a second transmission gate output, the second transmission gate output being a replica of the first NAND gate output when the first mode control signal is of the second logical state and the second mode control signal is of the first logical state, and the second transmission gate output being of high impedance when the first mode control signal is of a first logical state and the second mode control signal is of a second logical state; and a clocked flip-flop (41) responsive to the first transmission gate output and the second transmission gate output.

## Claims

### Claim 1

A flip-flop circuit comprising:
a first NAND gate responsive to a D input to the flip-flop circuit and a first mode control signal for providing a first NAND gate output;
a second NAND gate responsive to a serial scan input to the flip-flop circuit and a second mode control signal for providing a second NAND gate output;
an inverter responsive to said first NAND gate output for providing an inverter output;
first transmission means responsive to said first NAND gate output and said second NAND gate output for providing a first transmission output, said first transmission means output being a replica of said inverter output when said first mode control signal is of a first logical state and said second mode control signal is of a second logical state, and said first transmission means output being of high impedance when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state;
second transmission means responsive to said first NAND gate output and said second NAND gate output for providing a second transmission means output, said second transmission means output being a replica of said first NAND gate output when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state, and said second transmission means output being of high impedance when said first mode control signal is of a first logical state and said second mode control signal is of a second logical state;
a clocked D-type flip-flop responsive to said first transmission means output and said second transmission means output;
whereby (a) said clocked D-type flip-flop is responsive to said first transmission means output when said first mode control signal is of said first logical state and said second mode control signal is of said second logical state, and (b) said clocked D-type flip-flop is responsive to said second transmission means output when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state.

### Claim 2 (depends on 1)

The flip-flop circuit of claim 1 wherein said first transmission means comprises a first transmission gate, and wherein said second transmission means comprises a second transmission gate.

### Claim 3

A flip-flop circuit comprising:
a first NAND gate responsive to a D input to the flip-flop circuit and a first mode control signal for providing a first NAND gate output;
a second NAND gate responsive to a serial scan input to the flip-flop circuit and a second mode control signal for providing a second NAND gate output;
a clocked D-type flip-flop having an input for receiving a flip-flop input;
mode selection means responsive to said first NAND gate output and said second NAND gate output for providing between said first NAND gate output and said flip-flop input a path that (a) includes an inverter delay when said first mode control signal is of a second logical state and said second mode control signal is of a first logical state, said inverse replica of the D input (b) excludes said inverter delay when said first mode control signal is of said first logical state and said second mode control signal is of said second logical state, said replica of the D input.

### Claim 4 (depends on 3)

The flip-flop circuit of claim 3 wherein said mode selection means comprises:
an inverter responsive to said first NAND gate output for providing an inverter output;
first transmission means responsive to said first NAND gate output and said second NAND gate output for providing a first transmission output, said first transmission means output being a replica of said inverter output when said first mode control signal is of said first logical state and said second mode control signal is of said second logical state, and said first transmission means output being of high impedance when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state;
second transmission means responsive to said first NAND gate output and said second NAND gate output for providing a second transmission means output, said second transmission means output being a replica of said first NAND gate output when said first mode control signal is of the second logical state and said second mode control signal is of the first logical state, and said second transmission means output being of high impedance when said first mode control signal is of said first logical state and said second mode control signal is of said second logical state;
said first transmission gate output and said second transmission gate output being connected to said clocked D-type flip-flop input.

### Claim 5 (depends on 4)

The flip-flop circuit of claim 4 wherein said first transmission means comprises a first transmission gate, and wherein said second transmission means comprises a second transmission gate.