# US 5,708,374 A · Self-timed control circuit for self-resetting logic circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,374 A - Document ID: US5708374A - Status: Granted - Kind: A - Application number: 08/647,492 - Filed: 1996-05-14 - Granted: 1998-01-13 - Earliest claimed: 1995-08-21 - Assignees: International Business Machines Corporation - Inventors: Christopher McCall Durham; Peter Juergen Klim - Web page: https://patentgrep.com/patent/US5708374A ## CPC - H03K 19/17704: the logic functions being realised by the interconnection of rows and columns - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them. ## Claims ### Claim 1 A system for implementing handshaking of data signals, comprising: a first macro for providing a first data signal and a first valid signal; a second macro for providing a second data signal and a second valid signal; and means for maintaining said first and second data signals active until both of said first and second data signals have been received by a third macro and said means for maintaining selectively asserts a complete signal to the third macro in response to the first valid signal and the second valid signal. ### Claim 2 (depends on 1) The system as recited in claim 1, wherein said maintaining means further comprises a means for sending from said third macro to said first and second macros a complete signal indicating that said first and second data signals have been received by said third macro. ### Claim 3 (depends on 2) The system as recited in claim 2, wherein said sending means further comprises: circuitry for receiving a first valid signal accompanying said first data signal; circuitry for receiving a second valid signal accompanying said second data signal; and circuitry for sending said complete signal when said first and second valid signals are both received. ### Claim 4 (depends on 3) The system as recited in claim 3, wherein said maintaining means further comprises: circuitry for resetting a last stage of logic circuitry in said second macro in response to receipt of said complete signal. ### Claim 5 (depends on 1) The system as recited in claim 1, further comprising: means for resetting a first stage of logic circuitry in said third macro in response to receipt by said third macro of both of said first and second data signals. ### Claim 6 (depends on 5) The system as recited in claim 5, further comprising: means for resetting logic stages subsequent to said first stage in response to receipt by said third macro of both of said first and second data signals. ### Claim 7 (depends on 1) The system of claim 1 wherein said first, second and third macros are implemented in a self-timed design. ### Claim 8 (depends on 1) The system of claim 1 wherein said first macro comprises a first valid bit for providing the first valid signal. ### Claim 9 (depends on 1) The system of claim 1 wherein said first, second and third macros comprise a plurality of stages of domino logic circuitry. ### Claim 10 A system for implementing handshaking of data signals, comprising: a first macro for providing a first data signal and a first valid bit; a second macro for providing a second data signal and a second valid bit; and means for maintaining said first and second data signals active until both of said first and second data signals have been received by a third macro and said means for maintaining selectively asserts a complete signal to the third macro in response to the first valid bit and the second valid bit, wherein each of said first, second, and third macros comprises a plurality of stages of domino logic circuitry. ### Claim 11 (depends on 10) The system as recited in claim 10, further comprising means for causing said first and second macros to discontinue activations of said first and second data signals in response to receipt of said first and second data signals by said third macro. ### Claim 12 A system for implementing handshaking of data signals, comprising: means for receiving a first data signal and a first valid signal from a first source; means for generating a complete signal in response to the first valid signal; means for receiving a second data signal from a second source; means for maintaining said first and second data signals active until the complete signal and both of said first and second data signals have been received by a circuit having a plurality of stages of domino logic; and means for causing said first and second sources to discontinue activations of said first and second data signals when both the complete signal and said first and second data signals have been received. ### Claim 13 (depends on 12) The system of claim 12 wherein said means for generating the complete signal comprises a Mueller C-element. ### Claim 14 A system for implementing handshaking of data signals, comprising: a first source for providing a first data signal and a first valid signal; a second source for providing a second data signal; and means for maintaining said first and second data signals active until the first valid signal and both of said first and second data signals have been received by a destination which comprises a plurality of stages of domino logic circuitry which performs a logic function on said first and second data signals, the destination being coupled to the first source and the second source.