# US 5,708,304 A · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,304 A - Document ID: US5708304A - Status: Granted - Kind: A - Application number: 08/708,615 - Filed: 1996-09-05 - Granted: 1998-01-13 - Earliest claimed: 1996-03-27 - Assignees: Mitsubishi Denki Kabushiki Kaisha - Inventors: Yoshihiro Tomita - Web page: https://patentgrep.com/patent/US5708304A ## CPC - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/552: {comprising metals or metalloids, e.g. silver} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device is reduced in size and has a highly warp resistant structure. A sealing resin formed by transfer molding covers a whole semiconductor chip including pad electrodes, connecting bumps, an upper surface of a wiring board including a plurality of chip connecting patterns, a side surface of the wiring board, and a peripheral area of a lower surface of the wiring board surrounding an area where external electrode portions are located. The wiring board is substantially coextensive in an area with the semiconductor chip in plan configuration. The area occupied by the external electrode portions is smaller than the area occupied by the chip connecting patterns. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor chip having first and second major surfaces, and a plurality of pad electrodes on the second major surface; a wiring board having first and second major surfaces, the second major surface of said semiconductor chip facing the first major surface of said wiring board, said wiring board including a plurality of chip connecting patterns arranged on the first major surface of said wiring board in a first array having a first outer dimension extending from one outside edge of said first array to another, opposite outside edge of said first array, and a plurality of external electrode portions arranged on the second major surface of said wiring board in a second array having a second outer dimension extending from one outside edge of said second array to another, opposite outside edge of said second array, respective chip connecting patterns being electrically connected to corresponding external electrode portions and electrically connected to corresponding pad electrodes; and a resin covering said semiconductor chip including said plurality of pad electrodes, and the first major surface of said wiring board including said plurality of chip connecting patterns, wherein the second outer dimension is smaller than the first outer dimension. ### Claim 2 (depends on 1) The semiconductor device of claim 1 comprising: a plurality of connecting electrodes directly and respectively connected to corresponding pad electrodes, and respective chip connecting patterns directly connected to corresponding connecting electrodes. ### Claim 3 The A semiconductor device comprising; a semiconductor chip having first and second major surfaces, and a plurality of pad electrodes on the first major surface; a wiring board having first and second major surfaces, the second major surface of said semiconductor chip facing the first major surface of said wiring board, said wiring board including a plurality of chip connecting patterns on the first major surface of said wiring board, surrounding said semiconductor chip, and arranged in a first array having a first outer dimension extending from one outside edge of said first array to another, opposite outside edge of said first array, and a plurality of external electrode portions arranged on the second major surface of said wiring board in a second array having a second outer dimension extending from one outside edge of said second array to another, opposite outside edge of said second array, respective chip connecting patterns being electrically connected to corresponding external electrode portions and electrically connected to corresponding pad electrodes by bonded metal wires bonded to corresponding pads a respective wire bonding points; and a resin covering said semiconductor chip including said plurality of pad electrodes, the first major surface of said wiring board including said plurality of chip connecting patterns, and the bonded metal wires, wherein the second outer dimension is smaller than the first outer dimension, and a distance between an end of said wiring board and a wire bonding point nearest that end is shorter than a distance between that end of said wiring board and the external electrode portion nearest that end. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein said semiconductor chip contacts and is bonded to said wiring board. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein said resin is formed by transfer molding. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein a distance between an end of said wiring board and the outside edge of said first array is shorter than a distance between the end of said wiring board and the outside edge of said second array, and wherein said resin extends from a side surface of said wiring board and covers a part of the second major surface of said wiring board except where said second array is located. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein each of said plurality of external electrode portions comprises: a conductive pattern connected directly to the second major surface of said wiring board; and a substantially spherical external electrode connected directly to said conductive pattern. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein each of said plurality of external electrode portions includes a branch-like connecting pin. ### Claim 9 (depends on 3) The semiconductor device of claim 3, wherein said resin is formed by transfer molding. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein a distance between an end of said wiring board and the outside edge of said first array is shorter than a distance between the end of said wiring board and the outside edge of said second array, and wherein said resin extends from a side surface of said wiring board and covers a part of the second major surface of said wiring board except where said second array is located. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein each of said plurality of external electrode portions comprises: a conductive pattern connected directly to the second major surface of said wiring board; and a substantially spherical external electrode connected directly to said conductive pattern. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein each of said plurality of external electrode portions includes a branch-like connecting pin.