# US 5,708,303 A · Semiconductor device having damascene interconnects

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,708,303 A
- Document ID: US5708303A
- Status: Granted
- Kind: A
- Application number: 08/742,959
- Filed: 1996-11-01
- Granted: 1998-01-13
- Earliest claimed: 1994-09-15
- Assignees: Texas Instruments Incorporated
- Inventors: Shin-Puu Jeng
- Web page: https://patentgrep.com/patent/US5708303A

## CPC

- H10W 20/48: Insulating materials thereof
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop.

## Claims

### Claim 1

An interconnect structure in a semiconductor device comprising:
a semiconductor layer;
a first high-k layer above said semiconductor layer;
a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity; and
a second high-k layer above said plurality of interconnects.

### Claim 2 (depends on 1)

The device of claim 1, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein said plurality of interconnects are comprised of aluminum.

### Claim 4 (depends on 1)

The device of claim 1, wherein said device includes an insulating layer between said first high-k layer and said plurality of interconnects, wherein said insulating layer is comprised of a second low-k material.

### Claim 5 (depends on 1)

The device of claim 1, wherein said device includes an insulating layer between said plurality of interconnects and said second high-k layer, wherein said insulating layer is comprised of a second low-k material.

### Claim 6 (depends on 1)

The device of claim 1, wherein said plurality of interconnects are comprised of a damascene processed metal material.

### Claim 7 (depends on 4)

The device of claim 4, wherein said insulating layer is comprised of silicon dioxide.

### Claim 8 (depends on 5)

The device of claim 5, wherein said insulating layer is comprised of silicon dioxide.

### Claim 9

An interconnect structure in a semiconductor device comprising:
a semiconductor layer;
a first high-k layer above said semiconductor layer;
a first insulating layer above said first high-k layer; and
a plurality of interconnects above said first insulating layer with a first low-k material between said plurality of interconnects that are at a relatively close proximity.

### Claim 10 (depends on 9)

The device of claim 9, wherein said device further includes a second insulating layer above said plurality of interconnects.

### Claim 11 (depends on 10)

The device of claim 10, wherein said device further includes a second high-k layer above said second insulating layer.

### Claim 12 (depends on 9)

The device of claim 9, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.

### Claim 13 (depends on 9)

The device of claim 9, wherein said plurality of interconnects are comprised of aluminum.

### Claim 14 (depends on 9)

The device of claim 9, wherein said first insulating layer is comprised of silicon dioxide.

### Claim 15 (depends on 10)

The device of claim 10, wherein said second insulating layer is comprised of a second low-k material.

### Claim 16 (depends on 9)

The device of claim 9, wherein said plurality of interconnects are comprised of a damascene, processed metal material.

### Claim 17

An interconnect structure in a semiconductor device comprising:
a semiconductor layer;
a plurality of interconnects above said semiconductor layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity;
a first insulating layer around said plurality of interconnects; and
a first high-k layer above said plurality of interconnects.

### Claim 18 (depends on 17)

The device of claim 17, wherein said device further includes a second high-k layer above said semiconductor layer and below said plurality of interconnects.

### Claim 19 (depends on 18)

The device of claim 18, wherein said device further includes a second insulating layer above said semiconductor layer and below said second high-k layer.

### Claim 20 (depends on 17)

The device of claim 17, wherein said plurality of interconnects are comprised of a metal barrier layer, a metal layer and a metal cap layer.

### Claim 21 (depends on 17)

The device of claim 17, wherein said plurality of interconnects are comprised of aluminum.

### Claim 22 (depends on 17)

The device of claim 17, wherein said first insulating layer is comprised of silicon dioxide.

### Claim 23 (depends on 17)

The device of claim 17, wherein said device includes a second insulating layer above said first high-k layer, wherein said second insulating layer is comprised of a second low-k material.

### Claim 24 (depends on 17)

The device of claim 17, wherein said plurality of interconnects are comprised of a damascene processed metal material.

### Claim 25

An interconnect structure in a semiconductor device comprising:
a semiconductor layer;
a first high-k layer above said semiconductor layer;
a plurality of interconnects above said first high-k layer, with a first low-k material between said plurality of interconnects that are at a relatively close proximity;
an insulating layer around said plurality of interconnects; and
a second high-k layer above said insulating layer and said plurality of interconnects.