# US 5,708,298 A · Semiconductor memory module having double-sided stacked memory chip layout

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- Number: US 5,708,298 A
- Document ID: US5708298A
- Status: Granted
- Kind: A
- Application number: 08/763,469
- Filed: 1996-12-10
- Granted: 1998-01-13
- Earliest claimed: 1987-06-24
- Assignees: Hitachi, Ltd.; Hitachi Tobu Semiconductor, Ltd.; Akita Electronics Co., Ltd.
- Inventors: Watanabe Masayuki; Sugano Toshio; Tsukui Seiichiro; Ono Takashi; Wakashima Yoshiaki
- Web page: https://patentgrep.com/patent/US5708298A

## CPC

- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/00: Details of stores covered by group G11C11/00
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- H05K 1/141: {One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters (H05K1/142 and H05K1/147 take precedence)}
- H10W 70/453: {comprising flexible metallic tapes}
- H10W 72/701: {Tape-automated bond [TAB] connectors}
- H10W 90/00: Package configurations
- H05K 3/3447: Lead-in-hole components
- H05K 3/368: {parallel to each other (H05K3/361 takes precedence)}
- H05K 2201/10515: Stacked components
- H05K 2201/10681: Tape Carrier Package [TCP]; Flexible sheet connector
- H05K 2203/1572: Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
- H10W 70/40: Leadframes
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01255: {by using masks}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/077: {Connecting of TAB connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/251: {Materials}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

## Claims

### Claim 1

A semiconductor memory module comprising:
(a) a substrate having a plurality of wirings, a terminal, a first surface and a second surface opposite to said first surface;
(b) a first device disposed on said first surface of said substrate, said first device having a semiconductor memory chip and first leads, said first leads being electrically connected to said semiconductor memory chip;
(c) a second device disposed on said second surface of said substrate, said second device having a semiconductor memory chip and second leads, said second leads being electrically connected to said semiconductor memory chip; and
(d) a third device disposed on said first surface of said substrate and having third leads, a first one of said third leads being electrically connected to one of said first leads of said first device by a first one of said plurality of wirings, a second one of said third leads being electrically connected to one of said second leads of said second device by a second one of said plurality of wirings, a third one of said third leads being electrically connected to said terminal of said substrate by a third one of said plurality of wirings,
wherein said third device inputs a predetermined signal to said first and second devices, and wherein said first and second devices are positioned across from one another on either side of the substrate, such that a distance between said first and third device is substantially equal to a distance between said second and third device.

### Claim 2 (depends on 1)

A semiconductor memory module according to claim 1, wherein each of said first and second leads of said first and second devices includes electrical common leads and an electrical independent lead.

### Claim 3 (depends on 2)

A semiconductor memory module according to claim 2, wherein said electrical common leads includes address signal leads and data signal leads, and wherein said electrical independent lead includes a chip selecting signal lead.

### Claim 4 (depends on 3)

A semiconductor memory module according to claim 3, wherein each of said electrical common leads of said first and second leads are electrically connected to each other via wirings in through holes formed in said substrate.

### Claim 5 (depends on 1)

A semiconductor memory module according to claim 1, further comprising:
(e) a fourth device having a semiconductor memory chip and fourth leads, said fourth leads being electrically connected to said semiconductor memory chip;
(f) a fifth device having a semiconductor memory chip and fifth leads, said fifth leads being electrically connected to said semiconductor memory chip,
wherein said fourth device is stacked over said first device, and wherein said fifth device is stacked over said second device.

### Claim 6 (depends on 5)

A semiconductor memory module according to claim 5, wherein each of said first, second, fourth and fifth leads of said first, second, fourth and fifth devices includes electrical common leads and an electrical independent lead.

### Claim 7 (depends on 6)

A semiconductor memory module according to claim 6, wherein said electrical common leads includes address signal leads and data signal leads, and wherein said electrical independent lead includes a chip selecting signal lead.

### Claim 8 (depends on 7)

A semiconductor memory module according to claim 7, wherein each of said electrical common leads of said first and second leads are electrically connected to each other via wirings in through holes formed in said substrate.

### Claim 9 (depends on 8)

A semiconductor memory module according to claim 8, wherein said electrical common leads of said fourth leads of said fourth device are electrically connected to said electrical common leads of said first leads of said first device, and wherein said electrical common leads of said fifth leads of said fifth device are electrically connected to said electrical common leads of said second leads of said second device.

### Claim 10 (depends on 1)

A semiconductor memory module according to claim 1, wherein one ends of said first, second, fourth and fifth leads are electrically connected to external terminals formed in the corresponding semiconductor memory chips of said first, second, fourth and fifth devices respectively, by bump electrodes formed therebetween.

### Claim 11

A semiconductor memory module comprising:
(a) a substrate having a plurality of wirings, a terminal, a first surface and a second surface opposite to said first surface;
(b) a first device disposed on said first surface of said substrate, said first device having a semiconductor memory chip and first leads, said first leads being electrically connected to said semiconductor memory chip;
(c) a second device disposed on said second surface of said substrate, said second device having a semiconductor memory chip and second leads, said second leads being electronically connected to said semiconductor memory chip; and
(d) a third device disposed on said first surface of said substrate and having third leads, a first one of said third leads being electrically connected to one of said first leads of said first device by a first one of said plurality of wirings, a second one of said third leads being electrically connected to one of said second leads of said second device by a second one of said plurality of wirings, a third one of said third leads being electrically connected to said terminal of said substrate by a third one of said plurality of wirings,
wherein said third device inputs a predetermined signal to said first and second devices, and wherein said first and second devices are positioned on respective said first and second surfaces such that they are symmetrical with regard to said substrate.