# US 5,708,291 A · Silicide agglomeration fuse device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,291 A - Document ID: US5708291A - Status: Granted - Kind: A - Application number: 08/537,283 - Filed: 1995-09-29 - Granted: 1998-01-13 - Earliest claimed: 1995-09-29 - Assignees: Intel Corporation - Inventors: Mark T. Bohr; Mohsen Alavi - Web page: https://patentgrep.com/patent/US5708291A ## CPC - H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance. ## Claims ### Claim 1 A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections, the fusible link device comprising: a polysilicon layer having a first resistance; a silicide layer formed on the polysilicon layer, the silicide layer having a second resistance lower than the first resistance, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased; and nine contacts electrically coupled to either end of the silicide layer for receiving the programming potential. ### Claim 2 A fuse disposed on a semiconductor substrate, and having a first un-programmed resistance, the fuse comprising: a polysilicon layer; a silicide layer formed on the polysilicon layer, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide, layer, such that the resistance of the fuse can be selectively increased to a second programmed resistance; and nine contacts electrically coupled to either end of the silicide layer for receiving the programming potential. ### Claim 3 A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections, the fusible link device comprising: a polysilicon layer having a first resistance, the polysilicon layer including a first region doped n-type and at least a second region doped p-type to form at least one p-n junction in the polysilicon layer; and a silicide layer formed on the polysilicon layer, the silicide layer having a second resistance lower than the first resistance, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased. ### Claim 4 (depends on 1) The fusible link device as set forth in claim 1 further including at least first and second contacts electrically coupled to opposite ends of the silicide layer for receiving the programming potential. ### Claim 5 (depends on 4) The fusible link device as set forth in claim 4 wherein the contacts comprise tungsten plugs. ### Claim 6 (depends on 1) The fusible link device as set forth in claim 1 wherein the programming potential is approximately 2 volts. ### Claim 7 (depends on 1) The fusible link device as set forth in claim 1 wherein the silicide layer comprises TiSi.sub.2. ### Claim 8 (depends on 7) The fusible link device as set forth in claim 7 wherein the silicide layer is approximately 200-400 angstroms thick. ### Claim 9 (depends on 1) The fusible link device as set forth in claim 1 wherein the polysilicon layer is approximately 2500 angstroms thick. ### Claim 10 (depends on 1) The fusible link device as set forth in claim 1 wherein a sheet resistance of the polysilicon layer is greater than 500 ohms per square, and a sheet resistance of the silicide layer is 1-10 ohms per square. ### Claim 11 (depends on 1) The fusible link device as set forth in claim 1 wherein the polysilicon layer is formed of a polysilicon film and the silicide layer is formed of a silicide film. ### Claim 12 (depends on 1) The fusible link device as set forth in claim 1 wherein the fuse device comprises a fuse region, the fuse region having a length four to 25 times as long as a width of the fuse region. ### Claim 13 (depends on 12) The fusible link device as set forth in claim 12 wherein the width of the fuse region is approximately 0.22 microns. ### Claim 14 A fuse disposed on a semiconductor substrate, and having a first un-programmed resistance, the fuse comprising: a polysilicon layer, the polysilicon layer including a first region doped n-type and at least a second region doped p-type to form at least one p-n junction in the polysilicon layer; and a silicide layer formed on the polysilicon layer, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fuse can be selectively increased to a second programmed resistance. ### Claim 15 (depends on 14) The fuse as set forth in claim 14 further including first and second contacts electrically coupled to the silicide layer for receiving the programming potential. ### Claim 16 (depends on 15) The fuse as set forth in claim 15 wherein the contacts comprise tungsten plugs. ### Claim 17 (depends on 14) The fuse as set forth in claim 14 wherein the programming potential is approximately 2 volts. ### Claim 18 (depends on 14) The fuse as set forth in claim 14 wherein the silicide layer comprises TiSi.sub.2. ### Claim 19 (depends on 18) The fuse as set forth in claim 18 wherein the silicide layer is approximately 200-400 angstroms thick. ### Claim 20 (depends on 14) The fuse as set forth in claim 14 wherein the polysilicon layer is approximately 2500 angstroms thick. ### Claim 21 (depends on 14) The fuse as set forth in claim 14 wherein the second programmed resistance is at least 10 times the first un-programmed resistance. ### Claim 22 A method for forming a fuse comprising the steps of: forming a polysilicon layer on a semiconductor substrate; doping the polysilicon layer n-type; forming p-type regions in the n-type polysilicon layer such that the polysilicon layer includes at least one p-n junction; forming a silicide layer on the polysilicon layer; and forming contacts at either end of the silicide layer, the contacts being electrically coupled to the silicide layer such that a programming potential may be applied across them to program the fuse device.