# US 5,708,287 A · Power semiconductor device having an active layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,287 A - Document ID: US5708287A - Status: Granted - Kind: A - Application number: 08/564,449 - Filed: 1995-11-29 - Granted: 1998-01-13 - Earliest claimed: 1995-11-29 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Akio Nakagawa; Yoshihiro Yamaguchi; Tomoko Matsudai - Web page: https://patentgrep.com/patent/US5708287A ## CPC - H10D 86/01: Manufacture or treatment - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10P 90/1906: {Preparing SOI wafers} - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An n.sup.- -type silicon active layer having a thickness of 6 .mu.m or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the active layer. The two devices are insulated and isolated from each other through a trench. The bipolar transistor has an n-type well layer formed in the surface of the active layer. A p-type well layer is formed in the surface of the n-type well layer. The thickness of the n-type well layer under the p-type well layer is set to be 1 .mu.m or more. A first n.sup.+ -type diffusion layer is formed in the surface of the n-type well layer. A p.sup.+ -type diffusion layer and a second n.sup.+ -type diffusion layer are formed in the surface of the p-type well layer. The n-type well layer and the first n.sup.+ -type diffusion layer serve as a collector region. The p-type well layer and the p.sup.+ -type diffusion layer serve as a base region. The second n.sup.+ -type diffusion layer serves as an emitter region. ## Claims ### Claim 1 A power IC comprising: a support substrate having an insulating surface; a semiconductor active layer formed on said substrate, said active layer having a thickness which is set to be 6 .mu.m or less; a device isolation layer formed to reach the insulating surface from a surface of said active layer so as to divide said active layer into first, second and third areas insulated and isolated from each other; a low-withstand-voltage, npn-bipolar transistor formed in the first area; a high-withstand-voltage, second semiconductor device formed in the second area and a low-withstand-voltage, CMOS transistor formed in the third area, said npn-bipolar transistor comprising: a first main well layer of an n-type formed in a surface of said active layer; a first sub-well layer of a p-type formed in a surface of said main well layer, said first main well layer under said first sub-well layer having a thickness which is a set to be 1 .mu.m or more, said thickness of said active layer and said thickness of said first main well under said first sub-well being set so as to suppress a leakage current at high operating temperatures and maintaining a substantially maximum amplification factor of said npn-bipolar transistor by passing a current within said active layer and not through a separate low-resistance buried layer; a first emitter layer of the n-type formed in a surface of said first sub-well layer; a collector electrode formed on a surface of said first main well layer; a base electrode formed on a surface of said first sub-well layer; and an emitter electrode formed on a surface of said first emitter layer. ### Claim 2 (depends on 1) An IC according to claim 1, wherein said second semiconductor device comprises an IGBT. ### Claim 3 (depends on 1) An IC according to claim 1, wherein said second semiconductor device comprises a MOSFET. ### Claim 4 (depends on 1) An IC according to claim 1, further comprising a low-withstand-voltage, pnp-type bipolar transistor formed in a fourth area of said active layer, the fourth area being insulated and isolated from the first, second and third area, said pnp-type bipolar transistor comprising: a second main well layer of the n-type formed in a surface of said active layer; a second emitter and collector layer of the p-type formed in a surface of said second main well layer; a base electrode formed on a surface of said second main well layer; an emitter electrode formed on a surface of said second emitter layer; and a collector electrode formed on a surface of said second collector layer. ### Claim 5 (depends on 4) An IC according to claim 4, wherein said CMOS transistor comprises a third main well layer of the n-type and a fourth main well layer of the p-type which are formed in a surface of said active layer, and wherein said first, second and third main well layers are formed in the same step. ### Claim 6 (depends on 1) An IC according to claim 1, wherein said first main well layer under said first sub-well layer of said npn-bipolar transistor reaches the insulating surface. ### Claim 7 (depends on 1) An IC according to claim 1, wherein said npn-bipolar transistor further comprises: a first low-resistance layer of the n-type formed in a surface of said first main well layer; a second low-resistance layer of the p-type formed in a surface of said first sub-well layer; and a third low-resistance layer of the n-type formed in a surface of said first sub-well layer, said third low-resistance layer constituting said first emitter layer; wherein said collector, base, and emitter electrodes of said npn-bipolar transistor being respectively formed on said first, second, and third low-resistance layers. ### Claim 8 (depends on 7) An IC according to claim 7, wherein said third low-resistance layer is formed between said first and second low-resistance layers. ### Claim 9 (depends on 8) An IC according to claim 8, wherein said first low-resistance layer is formed to surround said first sub-well layer. ### Claim 10 (depends on 1) An IC according to claim 1, further comprising a fourth low-resistance layer of the p-type formed in a surface of said active layer of said npn-bipolar transistor to reach the insulating surface, wherein a potential for fixing a potential of said active layer is applied to said fourth low-resistance layer. ### Claim 11 A power IC comprising: a support substrate having an insulating surface; a semiconductor active layer formed on said substrate, said active layer having a thickness which is set to be 6 mm or less; a device isolation layer formed to reach the insulating surface from a surface of said active layer so as to divide said active layer into first, second and third areas insulated and isolated from each other; a low-withstand-voltage, pnp-bipolar transistor formed in the first area; a high-withstand-voltage, second semiconductor device formed in the second area; and a low-withstand-voltage, CMOS transistor formed in the third area, said pnp-bipolar transistor comprising: a first main well layer of an p-type formed in a surface of said active layer; a first sub-well layer of a n-type formed in a surface of said main well layer, said first main well layer under said first sub-well layer having a thickness which is a set to be 1mm or more, said thickness of said active layer and said thickness of said first main well under said first sub-well being set so as to suppress a leakage current at high operating temperatures and maintaining a substantially maximum amplification factor of said pnp-bipolar transistor by passing a current within said active layer and not through a separate low-resistance buried layer; a first emitter layer of the p-type formed in a surface of said first sub-well layer; a collector electrode formed on a surface of said first main well layer; a base electrode formed on a surface of said first sub-well layer; and an emitter electrode formed on a surface of said first emitter layer. ### Claim 12 (depends on 11) An IC according to claim 11, wherein said second semiconductor device comprises an insulated gate bipolar transistor. ### Claim 13 (depends on 11) An IC according to claim 11, wherein said second semiconductor device comprises a MOSFET. ### Claim 14 (depends on 11) An IC according to claim 11, wherein said first main well layer under said first sub-well layer of said pnp-bipolar transistor reaches the insulating surface. ### Claim 15 (depends on 11) An IC according to claim 11, wherein said pnp-bipolar transistor further comprises: a first low-resistance layer of the p-type formed in a surface of said first main well layer; a second low-resistance layer of the n-type formed in a surface of said first sub-well layer; and a third low-resistance layer of the p-type formed in a surface of said first sub-well layer, said third low-resistance layer constituting said first emitter layer, wherein said collector, base, and emitter electrodes of said pnp-bipolar transistor being respectively formed on said first, second, and third low-resistance layers. ### Claim 16 (depends on 11) An IC according to claim 11, wherein said support substrate comprises a backside layer made of silicon and an insulating layer made of a silicon oxide and formed on the backside layer, and the insulating surface is defined by a surface of the insulating layer. ### Claim 17 A power IC comprising: a support substrate having an insulating surface; a semiconductor active layer formed on said substrate, said active layer having a thickness which is set to be 6 .mu.m or less; a device isolation layer formed to reach the insulating surface from a surface of said active layer so as to divide said active layer into first, second and third areas insulated and isolated from each other; a low-withstand-voltage, pnp-bipolar transistor formed in the first area; a high-withstand-voltage, second semiconductor device formed in the second area; and a low-withstand-voltage, CMOS transistor formed in the third area, said pnp-bipolar transistor comprising: a main well layer of the n-type formed in a surface of said active layer; emitter and collector layers of the p-type formed in a surface of said main well layer and configured so as to maintain a substantially maximum amplification factor of said pnp-bipolar transistor by passing a current within said active layer and not through a separate low-resistance buried layer; a base electrode formed an a surface of said main well layer; an emitter electrode formed on a surface of said emitter layer; and a collector electrode formed on a surface of said collector layer. ### Claim 18 (depends on 17) An IC according to claim 17, wherein said pnp-bipolar transistor further comprises: a low-resistance layer of the n-type formed in a surface of said first main well layer, said base electrode being formed on said low-resistance layer. ### Claim 19 (depends on 18) An IC according to claim 18, wherein said low-resistance layer is formed between said emitter and collector layers. ### Claim 20 (depends on 19) An IC according to claim 19, wherein said collector layer is formed to surround said emitter layer with a cutout facing said low-resistance layer. ### Claim 21 (depends on 17) An IC according to claim 17, wherein said support substrate comprises a backside layer made of silicon and an insulating layer made of a silicon oxide and formed on the backside layer, and the insulating surface is defined by a surface of the insulating layer. ### Claim 22 (depends on 1) The IC according to claim 1, wherein said active layer has a substantially uniform thickness. ### Claim 23 (depends on 11) The IC according to claim 11, wherein said active layer has a substantially uniform thickness. ### Claim 24 (depends on 1) The IC according to claim 1, wherein said active layer has a substantially uniform thickness. ### Claim 25 (depends on 1) An IC according to claim 1, wherein said support substrate comprises a backside layer made of silicon and an insulating layer made of a silicon oxide and formed on the backside layer, and the insulating surface is defined by a surface of the insulating layer.