# US 5,708,286 A · Insulated gate semiconductor device and fabrication method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,708,286 A - Document ID: US5708286A - Status: Granted - Kind: A - Application number: 08/623,702 - Filed: 1996-03-29 - Granted: 1998-01-13 - Earliest claimed: 1995-03-31 - Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho - Inventors: Tsutomu Uesugi; Masahito Kodama - Web page: https://patentgrep.com/patent/US5708286A ## CPC - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A vertical semiconductor device having an insulated gate structure makes use of a double-gate structure. The double-gate structure dramatically reduces the channel resistance, JFET resistance, and epitaxial resistance of the on-resistance of the power MOSFET, and implements an adequate breakdown voltage due to the effect of gate bias. In principle, a first gate and second gate having mutually facing portions are driven synchronously. This causes first and second channels to be formed in correspondence with first and second gates, and the currents flowing through these first and second channels form the on-current for this power device having a vertical structure. ## Claims ### Claim 1 A vertical semiconductor device with an insulated gate structure comprising: a semiconductor substrate as a drain region; a channel region formed within the semiconductor substrate; a source region formed in contact with said channel region; and a first gate and a second gate formed on one surface side of the semiconductor substrate, said first and second gates being electrically insulated from the semiconductor substrate and having mutually opposing portions; wherein: first and second channels corresponding to said first and second gates are formed in said channel region by driving said first and second gates so that currents flow through said first and second channels from another surface side of the semiconductor substrate to said one surface side thereof; said first gate is provided on one surface of said semiconductor substrate and said second gate is formed within said semiconductor substrate to have a buried portion encased within said semiconductor substrate, said first gate and said buried portion of said second gate extending in substantially parallel directions with respect to said one surface of said semiconductor substrate: and a region interposed between said first gate and said buried portion of said second gate forms said channel region. ### Claim 2 (depends on 1) The vertical semiconductor device as defined in claim 1, wherein the thickness of said channel region in the vertical direction is less than the length of said first and second channels formed in said channel region. ### Claim 3 (depends on 1) The vertical semiconductor device as defined in claim 1, wherein a voltage of said second gate is fixed at a predetermined level when said insulated gate semiconductor device is in an off state. ### Claim 4 (depends on 1) The vertical semiconductor device as defined in claim 1, wherein: said second gate is provided with an electrode contact portion which is connected to said buried portion and which is partially exposed on part of said one surface of said semiconductor substrate, and an electrode for driving said second gate is formed on said one surface of said semiconductor substrate and is connected to said electrode contact portion. ### Claim 5 (depends on 1) The vertical semiconductor device as defined in claim 1 wherein said first and second gates are driven synchronously. ### Claim 6 (depends on 1) The vertical semiconductor device as defined in claim 1 wherein said channel region is completely depleted after said first and second channels have been formed. ### Claim 7 (depends on 1) The vertical semiconductor device as defined in claim 1 wherein said insulated gate semiconductor device is a power MOSFET. ### Claim 8 (depends on 1) The vertical semiconductor device as defined in claim 1 wherein said insulated gate semiconductor device is an insulated gate bipolar transistor (IGBT). ### Claim 9 (depends on 1) The vertical semiconductor device as defined in claim 1, wherein said semiconductor substrate comprises: a first substrate which is a high-concentration layer and has a drain electrode on a surface thereof; and a second substrate which is a low-concentration layer and has said buried portion of said second gate; wherein said first gate and said buried portion of said second gate are provided in parallel directions with respect to said first substrate, and at least one of said first gate and said buried portion of said second gate overlaps with said first substrate when said vertical semiconductor device is viewed in a direction perpendicular to said first substrate. ### Claim 10 (depends on 9) The vertical semiconductor device as defined in claim 9, wherein said second substrate includes a part of said drain region partially surrounded by said first gate and said two adjacent buried portions via an insulating film. ### Claim 11 (depends on 1) The vertical semiconductor device as claimed in claim 1, wherein said source region and said buried portion of said second gate overlap one another in a direction perpendicular to said semiconductor substrate.