# US 5,707,897 A · Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,707,897 A - Document ID: US5707897A - Status: Granted - Kind: A - Application number: 08/649,977 - Filed: 1996-05-16 - Granted: 1998-01-13 - Earliest claimed: 1996-05-16 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jin-Yuan Lee; Mong-Song Liang - Web page: https://patentgrep.com/patent/US5707897A ## CPC - H10B 41/30: characterised by the memory core region - H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode} - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method for making an improved Electrically Programmable Read-Only-Memory (EPROM) device having non-volatile memory cells with enhanced capacitive coupling was achieved. The array of memory cells consists of a single field effect transistor (FET) having an additional floating gate. The FET is formed in a well etched into an insulating layer on the substrate surface. After forming the FET gate oxide, a polysilicon layer is patterned to form a trench-like floating gate with increased capacitive coupling. An interlevel dielectric layer is deposited. A second polysilicon layer is deposited in the well and chem/mech polished back to form the control gate. The insulating layer having the wells is selectively removed. Lightly doped source/drain areas, self-aligned to the FET gate electrodes, are implanted and after forming sidewall spacers on the gate electrodes, source/drain contacts and buried bit lines are formed by a second implant. An insulating layer is deposited over the array of FETs having contact openings to the FET control gates. Another polysilicon layer is deposited and patterned to form the word lines. The word lines and buried bit lines are connected to the peripheral circuits to complete the EPROM chip. ## Claims ### Claim 1 A method of fabricating an array of non-volatile memory cells having enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of device areas into column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby completing said array of said non-volatile memory cells. ### Claim 2 (depends on 1) The method of claim 1, wherein said trenches in said silicon substrate are etched to a depth of about 3000 to 10000 Angstroms. ### Claim 3 (depends on 1) The method of claim 1, wherein said first insulating layer is deposited to a thickness of about 3000 to 15000 Angstroms. ### Claim 4 (depends on 1) The method of claim 1, wherein said second insulating layer is deposited to a thickness of about 2500 to 5000 Angstroms. ### Claim 5 (depends on 1) The method of claim 1, wherein said gate oxide is formed by thermal oxidation having a thickness of about 40 to 200 Angstroms. ### Claim 6 (depends on 1) The method of claim 1, wherein said first polysilicon layer is between about 300 to 1000 Angstroms thick. ### Claim 7 (depends on 1) The method of claim 1, wherein said interlevel dielectric insulating layer is about 50 to 100 Angstroms thick. ### Claim 8 (depends on 1) The method of claim 1, wherein said second polysilicon layer has a thickness of about 2500 to 4000 Angstroms. ### Claim 9 (depends on 1) The method of claim 1, wherein said lightly doped drains formed by ion implantation use an implant dose of about 1.0 E 13 to 5.0 E 13 ions/cm.sup.3, and ion implant energy of about 10 to 70 keV. ### Claim 10 (depends on 1) The method of claim 1, wherein said source/drain contact areas and said buried bit lines are formed by ion implantation using an implant dose of about 1.0 E 15 to 7.0 E 15 ions/cm.sup.3, and ion implant energy of about 10 to 70 keV. ### Claim 11 A method of fabricating an electrically programmable read only memory (EPROM) having memory cells with enhanced capacitive coupling, comprising the steps of: forming trenches in a silicon substrate by masking and anisotropic plasma etching; thermally oxidizing the surface of said trenches; depositing a conformal first insulating layer in said trenches and elsewhere on said silicon substrate; etching back said first insulating layer to the surface of said silicon substrate and thereby forming planar field oxide regions, wherein said field oxide regions electrically isolate an array of column device areas and row device areas on said substrate surface; depositing a second insulating layer on said field oxide regions and elsewhere on said device areas on said silicon substrate; forming wells in said second insulating layer to said substrate surface extending over said row device areas and also said wells extending over adjacent said field oxide regions and lying between said column device areas; thermally oxidizing said silicon substrate surface in said wells thereby forming a gate oxide for said non-volatile memory cells; depositing a conformal first polysilicon layer on said second insulating layer and in said wells; patterning said first polysilicon layer leaving portions in said wells and over opposite sidewalls parallel to said column device areas, and removing portions of said first polysilicon layer on other sidewalls parallel to said row device areas and on said field oxide regions adjacent to said row device areas thereby forming floating gates; depositing an interlevel dielectric insulating layer on said patterned first polysilicon layer and elsewhere on said second insulating layer; depositing a conformal second polysilicon layer over said dielectric insulating layer and in said wells thereby filling said wells; chemical/mechanical polishing back said second polysilicon layer and said dielectric insulating layer and said first polysilicon layer to the surface of said second insulating layer thereby forming the control gate electrodes for field effect transistors (FETs) from said second polysilicon layer; removing selectively said second insulating layer to said substrate thereby leaving an array of said gate electrodes having said floating gate and said control gate with increased surface area with enhanced capacitive coupling; doping said device areas adjacent to said electrodes by ion implantation thereby forming lightly doped drains; depositing a conformal third insulating layer over said gate electrodes and elsewhere on said substrate; anisotropically blanket etch back said third insulating layer forming sidewall spacers on said gate electrodes; doping said device areas and forming source/drain contact areas and buried bit lines in said column device areas on said substrate thereby forming said array of said memory cells; and further, depositing a conformal fourth insulating layer over said array of said memory cells and elsewhere on said substrate; etching contact openings in said fourth insulating layer to said control gate electrodes over said field oxide regions; depositing and patterning a third polysilicon layer thereby forming word lines contacting said control gate electrodes, said word lines and said bit lines contacting peripheral circuits thereby completing said EPROM. ### Claim 12 (depends on 11) The method of claim 11, wherein said trenches in said silicon substrate are etched to a depth of about 3000 to 10000 Angstroms. ### Claim 13 (depends on 11) The method of claim 11, wherein said first insulating layer is deposited to a thickness of about 3000 to 15000 Angstroms. ### Claim 14 (depends on 11) The method of claim 11, wherein said second insulating layer is deposited to a thickness of about 2500 to 5000 Angstroms. ### Claim 15 (depends on 11) The method of claim 11, wherein said gate oxide is formed by thermal oxidation having a thickness of about 40 to 200 Angstroms. ### Claim 16 (depends on 11) The method of claim 11, wherein said first polysilicon layer is between about 300 to 1000 Angstroms thick. ### Claim 17 (depends on 11) The method of claim 11, wherein said interlevel dielectric insulating layer is about 50 to 100 Angstroms thick. ### Claim 18 (depends on 11) The method of claim 11, wherein said second polysilicon layer has a thickness of about 2500 to 4000 Angstroms. ### Claim 19 (depends on 11) The method of claim 11, wherein said lightly doped drains formed by ion implantation use an implant dose of about 1.0 E 13 to 5.0 E 13 ions/cm.sup.3, and ion implant energy of about 10 to 70 keV. ### Claim 20 (depends on 11) The method of claim 11, wherein said source/drain contact areas and said buried bit lines are formed by ion implantation using an implant dose of about 1.0 E 15 to 7.0 E 15 ions/cm.sup.3, and ion implant energy of about 10 to 70 keV.