# US 5,707,895 A · Thin film transistor performance enhancement by water plasma treatment

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- Number: US 5,707,895 A
- Document ID: US5707895A
- Status: Granted
- Kind: A
- Application number: 08/734,559
- Filed: 1996-10-21
- Granted: 1998-01-13
- Earliest claimed: 1996-10-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shou-Gwo Wuu; Cheng-Yeh Shih; Kan-Yuan Lee
- Web page: https://patentgrep.com/patent/US5707895A

## CPC

- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10P 95/94: {Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma}
- Y10S 438/91: Controlling charging state at semiconductor-insulator interface
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A process is provided in which silicon thin film transistors fabricated with polycrystalline silicon, silicon oxide, and silicon conductive layers are exposed to microwave plasmas containing water vapor and to subsequent annealing steps to bring about an improvement in the ratio of device drain current in the conductive state to that in the non-conductive state, and a lower device subthreshold voltage swing.

## Claims

### Claim 1

A method for the fabrication of silicon-gate thin film field effect transistors with optimized device electrical parameters comprising:
depositing a polycrystalline silicon gate layer on an insulating substrate;
depositing a silicon oxide gate insulation layer on the silicon gate layer;
depositing a silicon conductive layer on the gate insulation layer;
forming of higher-conductivity regions by ion implantation into the conductive silicon layer to form the source and drain regions which define the device channel dimensions;
passivating already-deposited layers by covering them with a glass passivation layer;
etching of electrical contact holes through the glass passivation layer;
depositing and defining a pattern of conductive metal layer to form gate, source, and drain electrical contacts and interconnections;
exposing devices to electrical plasmas in a water vapor gaseous environment; and
annealing.

### Claim 2 (depends on 1)

The method of claim 1 wherein said polycrystalline silicon gate layer is between about 500 and 600 A thick.

### Claim 3 (depends on 1)

The method of claim 1 wherein said silicon oxide gate insulation layer is between about 200 to 400 A thick.

### Claim 4 (depends on 1)

The method of claim 1 wherein said amorphous silicon conductive layer is between about 200 to 400 A thick.

### Claim 5 (depends on 1)

The method of claim 1 wherein said glass passivation layer comprises a boro-phospho-silicate glass containing boron, phosphorus, and silicon.

### Claim 6 (depends on 4)

The method of claim 4 wherein said silicon layer is rendered more conductive by annealing at between about 500.degree. to 700.degree. C. for between about 10 to 24 hours.

### Claim 7 (depends on 1)

The method of claim 1 wherein said exposing devices to electrical plasma comprises a first passivation step and a second stripping step.

### Claim 8 (depends on 7)

The method of claim 7 wherein said first passivation step exposes said devices to a plasma process comprising:
maintaining devices in a reactor chamber at a holder temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in said water vapor gaseous environment at a pressure of between about 1.5 and 2.5 Torr and a gas flow rate of between about 400 to 600 standard cubic centimeters per second;
supplying microwave power to sustain said plasma at between about 1200 to 1600 watts at a frequency of 2.45 GEv; and
exposing devices to said plasma for between about 10 to 30 seconds.

### Claim 9 (depends on 7)

The method of claim 7 wherein said second stripping step exposes devices to plasma process comprising:
maintaining said devices in a reactor chamber at a holder temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in a gas mixture comprising water vapor, oxygen, and nitrogen at gas flow rates of about 200 to 400, 3000 to 4000, and 150 to 250 standard cubic centimeters per second respectively at a total gas pressure of about 1.5 to 2.5 Torr;
supplying microwave power to sustain said electrical plasma at between about 1200 to 1600 watts at a frequency of 2.45 GHz; and
exposing devices to said plasma for between about 150 to 210 minutes.

### Claim 10 (depends on 1)

The method of claim 1 wherein said anneal step is carried out in an environment of nitrogen gas for between about 20 to 40 minutes at a temperature of between about 225.degree. to 275.degree. C.

### Claim 11

A process for improving the electrical parameters of silicon-gate thin film transistor devices comprising:
fabricating said devices on an insulating substrate by successive deposition of silicon gate, silicon oxide gate insulation, and conductive silicon layers, annealing at between about 500.degree. to 700.degree. C. for between about 10 to 24 hours;
ion implanting, passivating, contact hole opening, and forming a metal pattern to produce complete devices;
exposing said devices to a first plasma passivation step in a water vapor environment, wherein said first plasma passivation step exposes said devices to a plasma process comprising:
maintaining said devices in a reactor chamber at a device holder temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in said water vapor environment comprising water vapor at a gas flow rate of between about 400 to 600 standard cubic centimeters per second and a total gas pressure of about 1.5 to 2.5 Torr;
supplying microwave power at between about 1200 to 1600 watts to the reactor at a frequency of 2.45 GHz to sustain the plasma; and
exposing said devices to said plasma for about 10 to 30 seconds;
exposing said devices to a second plasma stripping step in a water vapor environment; and
annealing of said devices.

### Claim 12 (depends on 11)

The process of claim 11 wherein said silicon gate layer is between about 500 to 600 A thick, said silicon oxide gate insulation layer is between about 200 to 400 A thick, and said conductive silicon layer is between about 200 to 400 A thick.

### Claim 13 (depends on 11)

The process of claim 11 wherein said conductive layer is annealed after deposition at between about 500.degree. to 700.degree. C. for between about 10 to 24 hours to increase conductivity.

### Claim 14 (depends on 11)

The process of claim 11 wherein said second plasma exposes said devices to a plasma process comprising;
maintaining said devices in a reactor chamber at a device holder stripping step
temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in a gas mixture comprising water vapor, oxygen, and nitrogen at gas flow rates of between about 200 to 400, 3000 to 4000, and 150 to 250 standard cubic centimeters per second respectively at a total gas pressure of about 2.0 Torr;
supplying microwave power to said reactor at between about 1200 to 1600 watts at a frequency of 2.45 GHz to sustain said plasma; and
exposing said devices to said plasma for between about 150 to 210 minutes.

### Claim 15 (depends on 11)

The process of claim 11 wherein said annealing of said devices is carded out in an atmosphere of nitrogen gas for between about 15 to 40 minutes at a temperature of between about 225.degree. to 275.degree. C.

### Claim 16

A method for the fabrication of silicon-gate thin film field effect transistors with optimized device electrical parameters comprising:
depositing a polycrystalline silicon gate layer on an insulating substrate;
depositing a silicon oxide gate insulation layer on the silicon gate layer;
depositing a silicon conductive layer on the gate insulation layer;
forming of higher-conductivity regions by ion implantation into the conductive silicon layer to form the source and drain regions which define the device channel dimensions;
passivating already-deposited layers by covering them with a glass passivation layer;
etching of electrical contact holes through the glass passivation layer;
depositing and defining a pattern of conductive metal layer to form gate, source, and drain electrical contacts and interconnections;
exposing devices to electrical plasmas, comprising a first passivation step and a second stripping step, wherein the first passivation step comprises:
maintaining devices in a reactor chamber at a holder temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in a water vapor gaseous environment at a pressure of between about 1.5 and 2.5 Torr and a gas flow rate of between about 400 to 600 standard cubic centimeters per second;
supplying microwave power to sustain said plasma at between about 1200 to 1600 watts at a frequency of 2.45 GEv; and
exposing devices to said plasma for between about 10 to 30 seconds; and
annealing.

### Claim 17 (depends on 16)

The method of claim 16 wherein said second stripping step exposes devices to plasma process comprising:
maintaining said devices in a reactor chamber at a holder temperature of between about 200.degree. to 240.degree. C.;
sustaining an electrical plasma therein in a gas mixture comprising water vapor, oxygen, and nitrogen at gas flow rates of about 200 to 400, 3000 to 4000, and 150 to 250 standard cubic centimeters per second respectively at a total gas pressure of about 1.5 to 2.5 Torr;
supplying microwave power to sustain said electrical plasma at between about 1200 to 1600 watts at a frequency of 2.45 GHz; and
exposing devices to said plasma for between about 150 to 210 minutes.