# US 5,707,893 A · Method of making a circuitized substrate using two different metallization processes

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- Number: US 5,707,893 A
- Document ID: US5707893A
- Status: Granted
- Kind: A
- Application number: 08/566,363
- Filed: 1995-12-01
- Granted: 1998-01-13
- Earliest claimed: 1995-12-01
- Assignees: International Business Machines Corporation
- Inventors: Anilkumar Chinuprasad Bhatt; Ashwinkumar Chinuprasad Bhatt; Robert Jeffrey Day; Thomas Patrick Duffy; Jeffrey Alan Knight; Richard William Malek; Voya Rista Markovich
- Web page: https://patentgrep.com/patent/US5707893A

## CPC

- H05K 1/0265: {characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections}
- H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)}
- H05K 3/428: {initial plating of through-holes in substrates having a metal pattern}
- H05K 1/0263: {High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board (H05K1/0293 takes precedence)}
- H05K 3/064: {Photoresists}
- H05K 2201/0347: Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
- H05K 2201/09727: Varying width along a single conductor; Conductors or pads having different widths
- H05K 2203/0353: Making conductive layer thin, e.g. by etching
- H05K 2203/072: Electroless plating, e.g. finish plating or initial plating
- H05K 2203/1407: Applying catalyst before applying plating resist
- Y10S 428/901: Printed circuit
- Y10T 428/24322: Composite web or sheet
- Y10T 428/24917: including metal layer
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A process for making a circuitized substrate is defined wherein the substrate is treated with two different, e.g., additive and subtractive, metallization processes. The process is thus able to effectively produce substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution in a cost effective and expeditious manner. The resulting product is also defined.

## Claims

### Claim 1

A method of making a circuitized substrate comprising the steps of:
providing a dielectric member including at least one dielectric layer having a first layer of electrically conductive material thereon;
forming a first electrically conductive member on said at least one dielectric layer of said dielectric member from said first layer of electrically conductive material using a first metallization process wherein some of said first layer of electrically conductive material is removed;
providing a second layer of electrically conductive material on said at least one dielectric layer including on said first electrically conductive member:
providing a second dielectric layer on said second layer of electrically conducting material and thereafter removing portions of said second dielectric layer to expose portions of said second layer of electrically conductive material, including over said first electrically conductive member; and
forming second electrically conductive members on said exposed portions of said second layer of said electrically conductive material using a second metallization process different from said first metallization process wherein electrically conductive material is added to said exposed portions of said second layer of electrically conductive material, including onto said second layer of electrically conductive material over said first electrically conductive member, thereby providing said circuitized substrate.

### Claim 2 (depends on 1)

The method of claim 1 wherein said second electrically conductive members are of a greater resolution than said first electrically conductive member.

### Claim 3 (depends on 1)

The method of claim 1 wherein said first layer of electrically conductive material is positioned on said dielectric member using a lamination process.

### Claim 4 (depends on 1)

The method of claim 1 wherein said first metallization process is a subtractive metallization process and said second metallization process is an additive metallization process.

### Claim 5 (depends on 1)

The method of claim 1 wherein said second layer of dielectric material is positioned on said first layer of electrically conductive material in the form of a sheet.

### Claim 6 (depends on 1)

The method of claim 1 wherein said some of said first layer of electrically conductive material is removed using an etching process.

### Claim 7 (depends on 1)

The method of claim 1 wherein said second dielectric layer is photoresist material, said removing of said portions of said second dielectric layer being accomplished using an exposure process in which selected regions of said photoresist are exposed and a development process in which said exposed selected regions are removed.

### Claim 8 (depends on 1)

The method of claim 1 further including providing at least one through-hole in said dielectric member, including through said at least one dielectric layer and said first layer of electrically conductive material, prior to the step of positioning said second dielectric layer, said second dielectric layer covering said through-hole.

### Claim 9 (depends on 8)

The method of claim 8 wherein said some of said first layer of electrically conductive material is removed using an etching process, said second dielectric layer covering said through-hole protecting said through-hole during said etching process.

### Claim 10 (depends on 1)

The method of claim 1 wherein said added electrically conductive material is added to said exposed portions of said second layer of electrically conductive material using an electroless plating process.

### Claim 11 (depends on 10)

The method of claim 10 wherein said electroless plating process comprises a plurality of dipping steps wherein said dielectric member is dipped in a plurality of different solutions, followed by a drying step in which said dielectric member is substantially dried.

### Claim 12 (depends on 1)

The method of claim 1 further including planarizing said second electrically conductive members.

### Claim 13 (depends on 12)

The method of claim 12 wherein said planarizing is accomplished using a mechanical process.

### Claim 14 (depends on 13)

The method of claim 13 wherein said mechanical process is sanding.

### Claim 15 (depends on 8)

The method of claim 8 wherein said at least one through-hole is provided using a drilling process.