# US 5,707,887 A · Method of manufacturing a non-volatile random accessible memory device

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- Number: US 5,707,887 A
- Document ID: US5707887A
- Status: Granted
- Kind: A
- Application number: 08/797,087
- Filed: 1997-02-10
- Granted: 1998-01-13
- Earliest claimed: 1992-05-26
- Assignees: Kappa Numerics, Inc.
- Inventors: Shimon Gendlin
- Web page: https://patentgrep.com/patent/US5707887A

## CPC

- H10D 1/68: Capacitors having no potential barriers
- B82Y 25/00: Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
- H01F 10/32: Spin-exchange-coupled multilayers, e.g. nanostructured superlattices {(applying spin-exchange-coupled multilayers to substrates H01F41/302)}
- Y10S 428/90: Magnetic feature
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A composition of materials having ferromagnetic, piezoelectric, and electro-optical properties is disclosed. In the preferred embodiment, the composition of materials comprises a first layer of Pb.sub.(1-x-y) Cd.sub.x Si.sub.y, a second layer of Se.sub.(1-z) S.sub.z, and a third layer of Fe.sub.(1-w) Cr.sub.w, where x, y, z and w are values within the ranges of 0.09.ltoreq.x.ltoreq.0.11, 0.09.ltoreq.y.ltoreq.0.11, 0.09.ltoreq.x.ltoreq.0.11 and 0.18.ltoreq.w.ltoreq.0.30. Additionally, each of the layers contain at least one of the elements of Ag, Bi, O, and N. A random-accessible, non-volatile memory built using the invented composition of materials is also disclosed. This memory provides for storing two independent bits of binary information in a single memory cell. Each cell comprises two orthogonal address lines formed on the opposite surface of a Si substrate, a composition of materials of the present invention formed over each of the address lines, and an electrode formed over each composition of materials. The data is stored electromagnetically and retrieved as a piezoelectric voltage.

## Claims

### Claim 1

A method of manufacturing a non-volatile, random-accessible memory device comprising the steps of:
forming a first address line on a first surface of a substrate;
forming a second address line on a second surface of the substrate;
forming a first composition of materials on the first address line and the first surface of the substrate, the first composition of materials having ferromagnetic and piezoelectric properties;
forming a second composition of materials on the second address line and the second surface of the substrate, the second composition of materials having ferromagnetic and piezoelectric properties.

### Claim 2 (depends on 1)

The method of claim 1 further comprising the steps of:
forming a first electrode on the first composition of materials; and
forming a second electrode on the second composition of materials.

### Claim 3 (depends on 1)

The method of claim 1 wherein the second address line is substantially orthogonal to the first address line.

### Claim 4 (depends on 1)

The method of claim 1 wherein the steps of forming each of the first and the second compositions of materials further comprises
forming a first layer of material having a composition of M.sub.(1-x-y) Cd.sub.x R.sub.y where M is an element selected from the group consisting of Pb, Zn, and Te, and R is an element selected from the group consisting of Si and Ge, wherein x and y are values within the ranges of 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.(x+y).ltoreq.1;
forming a second layer of Se.sub.(1-z) S.sub.z on the first layer, wherein z is a value within the range of 0.ltoreq.z.ltoreq.1; and
forming a third layer of Fe.sub.(1-w) Cr.sub.w on the second layer, wherein w is a value of 0.ltoreq.w.ltoreq.1.

### Claim 5 (depends on 4)

The method of claim 4 wherein the values of x, y, z, and w are within the ranges of 0.09.ltoreq.x.ltoreq.0.11, 0.09.ltoreq.y.ltoreq.0.11, 0.09.ltoreq.z.ltoreq.0.11, and 0.22.ltoreq.w.ltoreq.0.26.

### Claim 6 (depends on 5)

The method of claim 5 wherein the value of x is substantially 0.10, the value of y is substantially 0.10, the value of z is substantially 0.10, and the value of w is substantially 0.24.

### Claim 7 (depends on 4)

The method of claim 4 wherein the step of forming the address lines comprises depositing conductive layers onto the surfaces of the substrate and etching the conductive layers.