# US 5,706,463 A · Cache coherent computer system that minimizes invalidation and copyback operations > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,463 A - Document ID: US5706463A - Status: Granted - Kind: A - Application number: 08/854,418 - Filed: 1997-05-12 - Granted: 1998-01-06 - Earliest claimed: 1995-03-31 - Assignees: Sun Microsystems, Inc. - Inventors: Zahir Ebrahim; Satyanarayana Nishtala; William Van Loo; Kevin Normoyle; Leslie Kohn; Louis F. Coffin, III - Web page: https://patentgrep.com/patent/US5706463A ## CPC - G06F 12/0822: {Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831)} - G06F 12/0815: Cache consistency protocols - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state. ## Claims ### Claim 1 A computer system, comprising: shared memory having a plurality of read-only datablocks; first and second processor subsystems each having an external cache memory including external tags for datablocks stored in the external cache memory, wherein if a cache miss on a requested datablock to the external cache memory occurs the processor subsystem generates one of a read to share always request if the requested datablock is one of said plurality of read-only datablocks and a read to share request; and memory interconnect that enables access to the shared memory and that includes circuitry for receiving the read to share and the read to share always request, and for allowing the requested datablock to be stored in the external cache memory, and that causes the external tags for the requested datablock to indicate an exclusive state in response to the read to share request only if no other processor subsystem has a copy of the requested datablock, and that causes the external tags for the requested datablock to indicate a shared state in response to the read to share always request. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the memory interconnect maintains duplicate tags that correspond to the external tags and sets the duplicate tags that correspond to the external tags for the requested datablock to indicate a modified state in response to the read to share request and sets the duplicate tags that correspond to the external tags for the requested datablock to indicate the shared state in response to the read to share always request. ### Claim 3 (depends on 2) The computer system of claim 2, wherein the requested datablock is one of said plurality of read-only datablocks and contains instructions for the processor subsystem such that the processor subsystem generates the read to share always request rather than the read to share request. ### Claim 4 (depends on 2) The computer system of claim 2, wherein the processor subsystem in response to a read miss on the external cache generates the read to share always request if the requested datablock is one of said plurality of read-only datablocks and generates the read to share request otherwise. ### Claim 5 (depends on 4) The computer system of claim 4, wherein the circuitry that receives the read to share or the read to share always request comprises a system controller that accesses the duplicate tags via a snoop bus. ### Claim 6 (depends on 5) The computer system of claim 5, wherein the system controller causes the external tags for the requested datablock to indicate the exclusive state in response to the read to share request and causes the external tags for the datablock to indicate the shared state in response to the read to share always request by transferring a message to the processor subsystem via a control path coupling the system controller and the processor subsystem. ### Claim 7 A multi-processor computer system having a plurality of processor subsystems, comprising: shared memory having a plurality of read-only datablocks; a first processor subsystem having an external cache memory including external tags for datablocks stored in the cache memory and that maintains the external tags according to a first coherency protocol; and memory interconnect that enables access to the shared memory and that includes duplicate tags that correspond to the external tags and that maintains the duplicate tags according to a second coherency protocol; wherein the first processor subsystem generates a read to share always request that specifies one of said plurality of read-only datablocks if a cache miss on the specified read-only datablock to the external cache memory occurs, and wherein the memory interconnect in response to the read to share always request causes the external tags for the specified read-only datablock to indicate a shared state; and wherein the first processor subsystem generates a read to share request that specifies a requested datablock if a cache miss on the requested datablock to the external cache memory occurs and wherein the memory interconnect causes the external tags for the requested datablock to indicate an exclusive state in response to the read to share request only if no other processor subsystem has a copy of the requested datablock. ### Claim 8 (depends on 7) The computer system of claim 7, wherein the first coherency protocol is a MOESI coherency protocol and wherein the second coherency protocol is a MOSI coherency protocol. ### Claim 9 (depends on 7) The computer system of claim 7, wherein the memory interconnect sets the duplicate tags that correspond to the external tags for the requested datablock to indicate a modified state in response to the read to share request and sets the duplicate tags that correspond to the external tags for the specified read-only datablock to indicate the shared state in response to the read to share always request. ### Claim 10 (depends on 9) The computer system of claim 9, wherein the specified read-only datablock contains instructions for the processor subsystem such that the processor subsystem generates the read to share always request rather than the read to share request. ### Claim 11 (depends on 9) The computer system of claim 9, wherein the memory interconnect includes a system controller that accesses the duplicate tags via a snoop bus. ### Claim 12 (depends on 11) The computer of claim 11, wherein the system controller causes the external tags for the requested datablock to indicate the exclusive state in response to the read to share request and causes the external tags for the specified read-only data block to indicate the shared state in response to the read to share always request by transferring a message to the processor subsystem via a control path coupled between the system controller and the processor subsystem. ### Claim 13 (depends on 7) The computer system of claim 7, wherein the first coherency protocol is a MESI protocol and the second coherency protocol is a MSI protocol. ### Claim 14 A cache coherency method in a multi-processor computer system, comprising the steps of: maintaining external tags for datablocks stored in an external cache memory of a processor according to a first coherency protocol; maintaining duplicate tags that correspond to the external tags according to a second coherency protocol; and one of generating a read to share always request that specifies a datablock if a cache miss on the datablock to the external cache memory occurs and the datablock lies in a read-only location in a main memory, and causing the external tags for the datablock to indicate a shared state in response to the read to share always request, and generating a read to share request that specifies the datablock if a cache miss on the datablock to the external cache memory occurs, and causing the external tags for the datablock to indicate an exclusive state in response to the read to share request after determining that no other processor owns the datablock. ### Claim 15 (depends on 14) The method of claim 14, wherein the the first coherency protocol is a MOESI coherency protocol and the second coherency protocol is a MOSI coherency protocol. ### Claim 16 (depends on 14) The method of claim 14, further comprising the steps of setting the duplicate tags that correspond to the external tags for the datablock to indicate a modified state in response to the read to share request and setting the duplicate tags that correspond to the external tags for the datablock to indicate the shared state in response to the read to share always request. ### Claim 17 (depends on 16) The method of claim 16, wherein the read to share always request is generated if the datablock lies in a read-only location in main memory, and the read to share request is generated otherwise in response to a read miss. ### Claim 18 (depends on 16) The method of claim 16, wherein the datablock contains instructions for the processor such that the read to share always request rather than the read to share request is generated. ### Claim 19 (depends on 14) The method of claim 14, wherein the first coherency protocol is a MESI protocol and the second coherency protocol is a MSI protocol.