# US 5,706,459 A · Processor having a variable number of stages in a pipeline

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- Number: US 5,706,459 A
- Document ID: US5706459A
- Status: Granted
- Kind: A
- Application number: 08/367,494
- Filed: 1994-12-30
- Granted: 1998-01-06
- Earliest claimed: 1994-01-06
- Assignees: Fujitsu Limited
- Inventors: Sakurai Atsushi
- Web page: https://patentgrep.com/patent/US5706459A

## CPC

- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 9/3842: {Speculative instruction execution}
- G06F 9/3867: {using instruction pipelines}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor, having a variable number of stages in a pipeline, splits, during a pipeline process, an instruction fetch stage or a memory access stage during an instruction fetch or a memory access of operand data for an external memory. This enables a simultaneous operation for both inputting instruction data and outputting an address for a fetch of the succeeding instruction data or a simultaneous operation for both inputting operand data and outputting an address for an access of the succeeding operand data.

## Claims

### Claim 1

A processor having a variable stage number pipeline, comprising:
register means for registering operand data;
instruction fetch means for fetching an instruction from a memory accessed by the processor, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means either operand data obtained from said memory in said memory access stage or operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages; and
instruction fetch stage split means for splitting said instruction fetch stage into an instruction address output stage in which the instruction fetch means outputs to said memory an instruction address, and an instruction data input stage in which the instruction fetch means inputs from said memory input data corresponding to said instruction address.

### Claim 2 (depends on 1)

The processor having a variable stage number pipeline according to claim 1, further comprising:
instruction fetch stage split control means for controlling said instruction fetch stage split means to split said instruction fetch stage, upon fetching an instruction to an external memory connected to the processor, when said instruction fetch stage split means has not split said instruction fetch stage.

### Claim 3 (depends on 2)

The processor having a variable stage number pipeline according to claim 2, wherein:
said instruction fetch stage split control means controls said instruction fetch stage split means to unsplit said instruction fetch stage, upon generating a branch by executing a branch instruction and fetching an instruction from an internal memory having an access time shorter than that of said external memory, when said instruction fetch stage split means has split said instruction fetch stage.

### Claim 4 (depends on 1)

The processor having a variable stage number pipeline according to claim 1, further comprising:
instruction address output stage wait control means for putting said instruction address output stage in a wait status for a desired number of instruction cycles.

### Claim 5 (depends on 1)

The processor having a variable stage number pipeline according to claim 1, wherein:
said instruction fetch means executes an output operation for said instruction address in said instruction address output stage in parallel with an input operation for said instruction data corresponding to an instruction address outputted in a previous stage in said instruction data input stage.

### Claim 6

A processor having a variable stage number pipeline comprising:
register means for registering operand data;
instruction fetch means for fetching an instruction from a memory accessed by the processor, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means either operand data obtained from said memory in said memory access stage or operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
a pipeline having
instruction fetch stage data retaining means for retaining data for use in said instruction fetch stage,
instruction decode stage data retaining means for retaining data for use in said instruction decode stage,
instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
memory access stage data retaining means for retaining data for use in said memory access stage, and
write back stage data retaining means for retaining data for use in said write back stage; and
an instruction fetch stage split means for splitting said instruction fetch stage data retaining means into
instruction address output stage data retaining means for retaining data for use in said instruction address output stage in which an instruction address is outputted to said memory, and
instruction data input stage data retaining means for retaining data for use in said instruction data input stage in which data corresponding to said instruction address is inputted from said memory.

### Claim 7 (depends on 6)

The processor having a variable stage number pipeline according to claim 6, further comprising:
instruction fetch stage split control means for controlling said instruction fetch stage split means to split said instruction fetch stage data retaining means, upon fetching an instruction to an external memory connected to the processor, when said instruction fetch stage split means has not split said instruction fetch stage data retaining means.

### Claim 8 (depends on 7)

The processor having a variable stage number pipeline according to claim 7, wherein:
said instruction fetch stage split control means controls said instruction fetch stage split means to unsplit said instruction fetch stage data retaining means, upon generating a branch by executing a branch instruction and fetching an instruction from an internal memory having an access time shorter than that of said external memory, when said instruction fetch stage split means has split said instruction fetch stage data retaining means.

### Claim 9 (depends on 6)

The processor having a variable stage number pipeline according to claim 6, further comprising:
instruction address output stage wait control means for controlling said instruction address output stage data retaining means to wait for a desired number of instruction cycles in an output operation for data retained by said instruction address output stage data retaining means.

### Claim 10 (depends on 6)

The processor having a variable stage number pipeline according to claim 6, wherein:
said data retained by said instruction fetch stage data retaining means, said instruction decode stage data retaining means, said instruction execute stage data retaining means, said memory access stage data retaining means and said write back stage data retaining means in said pipeline are a program counter value.

### Claim 11

A processor having a variable stage number pipeline comprising:
first memory means for storing an instruction and operand data;
register means for registering said operand data;
instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages; and
memory access stage split means for splitting said memory access to stage into
an operand address output stage for outputting to said memory means an operand address and
an operand data read/write stage for accessing said memory means for reading/writing operand data corresponding to said operand address.

### Claim 12 (depends on 11)

The processor having a variable stage number pipeline according to claim 11, wherein:
said memory access stage split means also splits a control signal corresponding to each instruction shifted in said memory access means into a signal corresponding to an operand address output stage and a signal corresponding to an operand data read/write stage.

### Claim 13 (depends on 11)

The processor having a variable stage number pipeline according to claim 11, further comprising:
second memory means having an access time longer than that of said first memory means for storing said operand data;
memory access stage split control means for controlling said memory access stage split means to split said memory access stage, upon accessing for reading/writing said operand data from/to said second memory means, when said memory access stage split means has not split said memory access stage.

### Claim 14 (depends on 13)

The processor having a variable stage number pipeline according to claim 13, wherein:
said memory access stage split control means controls said memory access stage split means to unsplit said memory access stage, upon executing an instruction not accompanying a memory access and a memory access executed by a succeeding instruction for said first memory means when said memory access stage split means has split said memory access stage.

### Claim 15 (depends on 11)

The processor having a variable stage number pipeline according to claim 11, further comprising:
operand address output stage wait control means for putting said operand address output stage in a wait status for a desired number of instruction cycles.

### Claim 16 (depends on 11)

The processor having a variable stage number pipeline according to claim 11, wherein:
said memory access means executes an output operation for said operand address in said operand address output stage in parallel with a read/write operation for said operand data in said operand data read/write stage.

### Claim 17

A variable pipeline controller comprising:
first memory means for storing an instruction and operand data;
register means for registering said operand data;
instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
a pipeline having
memory access stage data retaining means for retaining data for use in said memory access stage,
instruction decode stage retaining means for retaining data for use in said instruction decode stage,
instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
memory access stage data retaining means for retaining data for use in said memory access stage, and
write back stage data retaining means for retaining data for use in said write back stage; and
memory access stage split means for splitting said memory access stage data retaining means into
operand address output stage data retaining means for retaining data for use in said operand address output stage for outputting to said first memory means an operand address, and
an operand data read/write stage data retaining means for retaining data for use in said operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

### Claim 18 (depends on 17)

The variable length pipeline controller according to claim 17, further comprising:
second memory means having an access time longer than that of said first memory for storing said operand data; and
a memory access stage split control means for controlling said memory access stage split means to split said memory access stage data retaining means, upon accessing for reading/writing said operand data from/to said second memory means, when said memory access stage split means has not split said memory access stage data retaining means.

### Claim 19 (depends on 18)

The variable length pipeline controller according to claim 18, wherein:
said memory access stage split control means controls said memory access stage split means to unsplit said memory access stage data retaining means, upon executing an instruction not accompanying a memory access and a memory access executed by a succeeding instruction is for said first memory means, when said memory access stage split means has split said memory access stage data retaining means.

### Claim 20 (depends on 17)

The variable length pipeline controller according to claim 17, comprising:
operand address output stage wait control means for having said operand address output stage data retaining means wait for a desired number of instruction cycles in an output operation for data retained by said operand address output stage data retaining means.

### Claim 21 (depends on 17)

The variable length pipeline controller according to claim 17, wherein:
said data retained by said memory access stage data retaining means are a program counter value.

### Claim 22

A variable length pipeline controller comprising:
first memory means for storing an instruction and operand data;
register means for registering said operand data;
instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
instruction fetch stage split means for splitting said instruction fetch stage into
an instruction address output stage for outputting to said first memory means an instruction address, and
an instruction data input stage for inputting from said first memory means input data corresponding to said instruction address; and
memory access stage split means for splitting said memory access stage into
an operand address output stage for outputting to said first memory means an operand address, and
an operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

### Claim 23 (depends on 22)

The variable length pipeline controller according to claim 22, further comprising:
second memory means having an access time longer than that of said first memory means for storing an instruction; and
an instruction fetch stage split control means for controlling said instruction fetch stage split means to split said instruction fetch stage, upon fetching an instruction to said second memory means, when said instruction fetch stage split means has not split said instruction fetch stage.

### Claim 24 (depends on 23)

The variable length pipeline controller according to claim 23, wherein:
said instruction fetch stage split control means controls said instruction fetch stage split means to unsplit said instruction fetch stage, upon generating a branch by executing a branch instruction and fetching an instruction from said first memory means, when said instruction fetch stage split means has split said instruction fetch stage.

### Claim 25 (depends on 22)

The variable length pipeline controller according to claim 22, further comprising:
second memory means having an access time longer than that of said first memory means for storing said operand data; and
a memory access stage split control means for controlling said memory access stage split means to split said memory access stage, upon accessing for reading/writing said operand data from/to said second memory means, when said memory access stage split means has not split said memory access stage.

### Claim 26 (depends on 25)

The variable length pipeline controller according to claim 25, wherein:
said memory access stage split control means controls said memory access stage split means to unsplit said memory access stage, upon executing an instruction not accompanying a memory access and a memory access executed by a succeeding instruction is for said first memory means, when said memory access stage split means has split said memory access stage.

### Claim 27 (depends on 22)

The variable length pipeline controller according to claim 22, further comprising:
instruction address output stage wait control means for putting said instruction address output stage in a wait status for a desired number of instruction cycles; and
operand address output stage wait control means for putting said operand address output stage in a wait status for a desired number of instruction cycles.

### Claim 28 (depends on 22)

The variable length pipeline controller according to claim 22, wherein:
said instruction fetch means executes an output operation for said instruction address in said instruction address output stage in parallel with an input operation for said instruction data in said instruction data input stage; and
said memory access means executes an output operation for said operand address in said operand address output stage in parallel with a read/write operation for said operand data in said operand data read/write stage.

### Claim 29

A variable length pipeline controller comprising:
first memory means for storing an instruction and operand data;
register means for registering said operand data;
instruction fetch means for fetching said instruction from said memory means, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory means at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into said register means one of said operand data obtained from said memory means in said memory access stage and said operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages;
a pipeline having
instruction fetch stage data retaining means for retaining data for use in said instruction fetch stage,
instruction decode stage data retaining means for retaining data for use in said instruction decode stage,
instruction execute stage data retaining means for retaining data for use in said instruction execute stage,
memory access stage data retaining means for retaining data for use in said memory access stage, and
write back stage data retaining means for retaining data for use in said write back stage;
instruction fetch stage split means for splitting said instruction fetch stage data retaining means into
instruction address output stage data retaining means for retaining data for use in said instruction address output stage for outputting to said first memory means an instruction address, and
instruction data input stage data retaining means for retaining data for use in said instruction data input stage for inputting from said first memory means input data corresponding to said instruction address; and
memory access stage split means for splitting said memory access stage data retaining means into
operand address output stage data retaining means for retaining data for use in said operand address output stage for outputting to said first memory means an operand address, and
an operand data read/write stage data retaining means for retaining data for use in said operand data read/write stage for accessing said first memory means for reading/writing operand data corresponding to said operand address.

### Claim 30 (depends on 29)

The variable length pipeline controller according to claim 29, further comprising:
second memory means having an access time longer than that of said first memory means for storing an instruction; and
instruction fetch stage split control means for controlling said instruction fetch stage split means to split said instruction fetch stage data retaining means, upon fetching an instruction to said second memory means, when said instruction fetch stage split means has not split said instruction fetch stage data retaining means.

### Claim 31 (depends on 30)

The variable length pipeline controller according to claim 30, wherein:
said instruction fetch stage split control means controls said instruction fetch stage split means to unsplit said instruction fetch stage data retaining means, upon generating a branch by executing a branch instruction and fetching an instruction from said first memory means, when said instruction fetch stage split means has split said instruction fetch stage data retaining means.

### Claim 32 (depends on 29)

The variable length pipeline controller according to claim 29, further comprising:
second memory means having an access time longer than that of said first memory means for storing operand data; and
memory access stage split control means for controlling said memory access stage split means to split said memory access stage data retaining means, upon accessing for reading/writing said operand data from/to said second memory means, when said memory access stage split means has not split said memory access stage data retaining means.

### Claim 33 (depends on 32)

The variable length pipeline controller according to claim 32, wherein:
said memory access stage split control means controls said memory access stage split means to unsplit said memory access stage data retaining means, upon executing an instruction not accompanying a memory access and a memory access executed by a succeeding instruction is for said first memory means, when said memory access stage split means has split said memory access stage data retaining means.

### Claim 34 (depends on 29)

The variable length pipeline controller according to claim 29 further comprising:
instruction address output stage wait control means for having said instruction address output stage data retaining means wait for a desired number of instruction cycles in an output operation for data retained by said instruction address output stage data retaining means; and
operand address output stage wait control means for having said operand address output stage data retaining means wait for a desired number of instruction cycles in an output operation for data retained by said operand address output stage data retaining means.

### Claim 35 (depends on 29)

The variable length pipeline controller according to claim 29, wherein:
said data retained by said pipeline are a program counter value.

### Claim 36

A pipeline processing method for use in a processor apparatus having a pipeline function, comprising:
an instruction address output stage of outputting an address for fetching a first instruction;
an instruction data input stage of outputting an address for fetching a second instruction and of inputting data at said first instruction;
an instruction decode stage of decoding said first instruction inputted in said instruction data input stage;
an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
a memory access stage of either reading or writing data at an address calculated from said first instruction executed in said instruction execute stage, when said first instruction is an instruction for either one of reading from and writing to a memory said operand data; and
a write back stage of writing data into an register, when said first instruction is an instruction for writing said data into said register.

### Claim 37

A pipeline process method for use in a processor apparatus having a pipeline function, comprising:
an instruction fetch stage of fetching a first instruction;
an instruction decode stage of decoding said first instruction fetched in said instruction fetch stage;
an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
an operand address output stage for outputting an address calculated from said first instruction executed in said instruction execute stage;
an operand data read/write stage of outputting an address calculated by executing a second instruction, when said second instruction is an instruction for either one of reading from and writing to a memory said operand data; and
a write back stage of writing data into a register, when said first instruction is an instruction for writing said data into said register.

### Claim 38

A pipeline processing method for use in a processor apparatus having a pipeline function, comprising:
an instruction address output stage of outputting an address for fetching a first instruction;
an instruction data input stage of outputting an address for fetching a second instruction and of inputting data on said first instruction;
an instruction decode stage of decoding said first instruction inputted in said instruction address input stage;
an instruction execute stage of executing said first instruction decoded in said instruction decode stage;
an operand address output stage for outputting an address calculated from said first instruction executed in said instruction execute stage;
an operand data read/write stage of outputting an address calculated by executing a second instruction, when said second instruction is an instruction for either one of reading from and writing to a memory operand data; and
a write back stage of writing data into a register, when said first instruction is an instruction for writing said data into said register.

### Claim 39

A variable stage number pipeline controller for use in a processor comprising:
instructions fetch means for fetching an instruction from a memory accessed by the processor, in an instruction fetch stage executable in parallel with other stages;
instruction decode means for decoding said instruction fetched in said instruction fetch stage, in an instruction decode stage executable in parallel with other stages;
instruction execute means for executing said instruction decoded in said instruction decode stage, in an instruction execute stage executable in parallel with other stages;
memory access means for accessing for a read/write operation said memory at an address calculated in said instruction execute stage, in a memory access stage executable in parallel with other stages;
write back means for writing into a register equipped with the processor either operand data obtained from said memory in said memory access stage or operand data processed in said instruction execute stage, in a write back stage executable in parallel with other stages; and
instruction fetch stage split means for splitting said instruction fetch stage into an instruction address output stage in which the instruction fetch means outputs to said memory an instruction address, and an instruction data input stage in which the instruction fetch means is inputted from said memory input data corresponding to said instruction address.

### Claim 40 (depends on 39)

The variable stage number pipeline controller for use in a processor according to claim 39, further comprising:
instruction fetch stage split control means for controlling said instruction fetch stage split means to split said instruction fetch stage, upon fetching an instruction to an external memory connected to the processor, when said instruction fetch stage split means has not split said instruction fetch stage.

### Claim 41 (depends on 39)

The variable stage number pipeline controller for use in a processor according to claim 39, wherein:
said instruction fetch stage split control means controls said instruction fetch stage split means to unsplit said instruction fetch stage, upon generating a branch by executing a branch instruction and fetching an instruction from an internal memory having an access time shorter than that of said external memory, when said instruction fetch stage split means has split said instruction fetch stage.

### Claim 42 (depends on 39)

The variable stage number pipeline controller for use in a processor according to claim 39, further comprising:
instruction address output stage wait control means for putting said instruction address output stage in a wait status for a desired number of instruction cycles.

### Claim 43 (depends on 39)

The variable stage number pipeline controller for use in a processor according to claim 39, wherein:
said instruction fetch means executes an output operation for said instruction address in said instruction address output stage in parallel with an input operation for said instruction data corresponding to instruction address outputted in a previous stage in said instruction data input stage.