Super pipelined speculative execution vector generator
AssigneeHewlett-Packard Company
InventorMonish S. Shah
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Abstract
A circuit and method for iterative generation of the variables used in vector generation and linear interpolation. Most significant bits are added in a last pipeline stage. Less significant bits are added in earlier pipeline stages. Breaking addition into multiple parts with each part having fewer bits to add enables a faster iterative cycle rate compared to a single long adder. Part of the vector generation algorithm requires a decision step based on the sign of the complete addition. Since this sign is generated in the last stage of the pipeline, it is not available at the time needed by earlier stages of the pipeline. Therefore, all possible combinations of outcomes for earlier pipeline stages are simultaneously speculatively computed for use by following pipeline stages.
Claims4
A circuit for iterative generation of a decision variable used in vector generation, the decision variable comprising most significant bits, less significant bits and a sign bit, the circuit comprising:
- at least two pipeline stages, one of the pipeline stages being a last pipeline stage and another one of the pipeline stages being a next-to-last pipeline stage;
- an adder in the last pipeline stage, receiving a carry input bit, adding the most significant bits and generating the sign bit as an output;
- two adders in the next-to-last pipeline stage, receiving the less significant bits and generating two speculative carry output bits;
- and
- the sign bit from the last pipeline stage being used to select one of the two speculative carry output bits of the next-to-last pipeline stage to be received as the carry input bit for the last pipeline stage.
A method of computing a decision variable used in iterative vector generation, the decision variable comprising a sign bit, most significant bits and less significant bits, the method comprising the following steps:
- generating the most significant bits and the sign bit in a last pipeline stage;
- receiving a carry input bit by the last pipeline stage;
- generating first and second speculative carry bits in a next-to-last pipeline stage;
- using the sign bit from the last pipeline stage to determine which of the first and second speculative carry bits from the next-to-last pipeline stage is received as the carry input bit by the last pipeline stage.
Dependencies are inferred from the claim text.