# US 5,706,323 A · Dynamic 1-of-2.sup.N logic encoding > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,706,323 A - Document ID: US5706323A - Status: Granted - Kind: A - Application number: 08/609,305 - Filed: 1996-03-01 - Granted: 1998-01-06 - Earliest claimed: 1996-03-01 - Assignees: Hewlett-Packard Company - Inventors: Robert H. Miller - Web page: https://patentgrep.com/patent/US5706323A ## CPC - G11C 8/10: Decoders - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)} - H03M 7/005: {using semiconductor devices} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A system of encoding a plurality of logic paths. A number of logic paths are subdivided into groups of N, N being greater than one. Each group of N logic paths is encoded such that an assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted. Simultaneous assertion of more than one of the 2.sup.N signal lines is defined as an invalid state. A simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines for dynamic operation. 1-of-2.sup.N encoding enables transmission of N variables by firing one out of N wires (rather than every wire, as in static logic, or one out of two wires, as in mousetrap logic). Signal degradation due to noise and coupling is reduced. In a multiplexer, 1-of-2.sup.N encoding reduces the load on the multiplexer's shift lines. Several 1-of-2.sup.N encoded multiplexers may be interconnected to form a self-timed dynamic shift register comprising one or more stages of tiered multiplexers. 1-of-2.sup.N encoding enables closer wire routings within such a shift register. Furthermore, 1-of-2.sup.N encoding can reduce the number of multiplexers required to implement a shift function. ## Claims ### Claim 1 A method of encoding a plurality of logic paths, the method comprising the steps of: a) subdividing the logic paths into groups of N logic paths, N being greater than one; b) encoding each group of N logic paths such that, i) assertion of a given combination of the N logic paths results in a predetermined one out of 2.sup.N signal lines being asserted; ii) a simultaneous assertion of more than one of the 2.sup.N signal lines is defined as invalid; and iii) a simultaneous non-assertion of all of the 2.sup.N signal lines enables precharging of the signal lines. ### Claim 2 (depends on 1) A method as in claim 1, wherein each of the signal lines is a buffered output line. ### Claim 3 (depends on 2) A method as in claim 2 wherein the step of encoding each group of N logic paths comprises the steps of: a) connecting a precharge/evaluation circuit to each of the buffered output lines; and b) connecting ANDed combinations of logic paths to each of the buffered output lines. ### Claim 4 (depends on 1) A method as in claim 1, wherein each logic path comprises high and low mousetrap lines. ### Claim 5 (depends on 1) A method as in claim 1, wherein N=2. ### Claim 6 A self-timed dynamic shift register comprising one or more stages of tiered multiplexers coupled to perform a shift function, each of said multiplexers comprising a plurality of data inputs and shift amount inputs, wherein various of said inputs comprise groups of 2.sup.N signal wires, N being an integer greater than one which is equal to a number of variables encoded in 1-of-2.sup.N format on a group of 2.sup.N signal wires. ### Claim 7 (depends on 6) A self-timed dynamic shift register as in claim 6, wherein only a number of said shift amount inputs comprise groups of 2.sup.N signal wires. ### Claim 8 (depends on 6) A self-timed dynamic shift register as in claim 6, wherein only a number of said data inputs comprise groups of 2.sup.N signal wires. ### Claim 9 (depends on 6) A self-timed dynamic shift register as in claim 6, wherein all of said inputs comprise groups of 2.sup.N signal wires. ### Claim 10 (depends on 6) A self-timed dynamic shift register as in claim 6, wherein the shift register comprises first, second and third stages of tiered multiplexers, each stage comprising a plurality of multiplexers, wherein the data inputs of said third stage do not comprise groups of 2.sup.N signal wires. ### Claim 11 (depends on 10) A self-timed dynamic shift register as in claim 10, further comprising means to convert data entering the third stage of multiplexers from 1-of-2.sup.N format to either mousetrap/dual-rail or single rail form. ### Claim 12 (depends on 11) A self-timed dynamic shift register as in claim 11, wherein the conversion means comprises logic within the second stage of multiplexers. ### Claim 13 (depends on 6) A self-timed dynamic shift register as in claim 6, wherein N=2. ### Claim 14 A multiplexer comprising a plurality of data inputs and shift amount inputs, each input comprising a group of 2.sup.N signal wires, N being an integer greater than one which is equal to a number of variables encoded in 1-of-2.sup.N format on a group of 2.sup.N signal wires. ### Claim 15 (depends on 14) A multiplexer as in claim 14, wherein N=2.